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git01.mediatek.com / filogic / uboot / 473bbc44192a45350726fd473d193a9bdf9ea387 / . / arch / arm / cpu / armv8 / fsl-layerscape / ls1043_ids.c
blob: 3bd993bebfbc0ee85cca479a53f29ebf8a5e6dd8 [file] [log] [blame]
Laurentiu Tudor22012d52018-08-27 17:33:59 +0300[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018 NXP
4 */
5
6#include <common.h>
7#include <asm/arch-fsl-layerscape/immap_lsch2.h>
8#include <asm/arch-fsl-layerscape/fsl_icid.h>
9#include <asm/arch-fsl-layerscape/fsl_portals.h>
10#include <fsl_sec.h>
11
12#ifdef CONFIG_SYS_DPAA_QBMAN
13struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
14 SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
15 SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
16 SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
17 SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
18 SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
19 SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
20 SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
21 SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
22 SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
23 SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
24};
25#endif
26
27struct icid_id_table icid_tbl[] = {
28#ifdef CONFIG_SYS_DPAA_QBMAN
29 SET_QMAN_ICID(FSL_DPAA1_STREAM_ID_START),
30 SET_BMAN_ICID(FSL_DPAA1_STREAM_ID_START + 1),
31#endif
32
33 SET_SDHC_ICID(FSL_SDHC_STREAM_ID),
34
35 SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
36 SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
37 SET_USB_ICID(3, "snps,dwc3", FSL_USB3_STREAM_ID),
38
39 SET_SATA_ICID("fsl,ls1043a-ahci", FSL_SATA_STREAM_ID),
40 SET_QDMA_ICID("fsl,ls1043a-qdma", FSL_QDMA_STREAM_ID),
41 SET_EDMA_ICID(FSL_EDMA_STREAM_ID),
42 SET_ETR_ICID(FSL_ETR_STREAM_ID),
43 SET_DEBUG_ICID(FSL_DEBUG_STREAM_ID),
44 SET_QE_ICID(FSL_QE_STREAM_ID),
45#ifdef CONFIG_FSL_CAAM
Laurentiu Tudor8aee3d62019-02-26 13:18:33 +0200[diff] [blame]46 SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_END),
Laurentiu Tudor22012d52018-08-27 17:33:59 +0300[diff] [blame]47 SET_SEC_JR_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 3),
48 SET_SEC_JR_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 4),
49 SET_SEC_JR_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 5),
50 SET_SEC_JR_ICID_ENTRY(3, FSL_DPAA1_STREAM_ID_START + 6),
51 SET_SEC_RTIC_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 7),
52 SET_SEC_RTIC_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 8),
53 SET_SEC_RTIC_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 9),
54 SET_SEC_RTIC_ICID_ENTRY(3, FSL_DPAA1_STREAM_ID_START + 10),
55 SET_SEC_DECO_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 11),
56 SET_SEC_DECO_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 12),
57#endif
58};
59
60int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
61
62#ifdef CONFIG_SYS_DPAA_FMAN
63struct fman_icid_id_table fman_icid_tbl[] = {
64 /* port id, icid */
65 SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END),
66 SET_FMAN_ICID_ENTRY(0x03, FSL_DPAA1_STREAM_ID_END),
67 SET_FMAN_ICID_ENTRY(0x04, FSL_DPAA1_STREAM_ID_END),
68 SET_FMAN_ICID_ENTRY(0x05, FSL_DPAA1_STREAM_ID_END),
69 SET_FMAN_ICID_ENTRY(0x06, FSL_DPAA1_STREAM_ID_END),
70 SET_FMAN_ICID_ENTRY(0x07, FSL_DPAA1_STREAM_ID_END),
71 SET_FMAN_ICID_ENTRY(0x08, FSL_DPAA1_STREAM_ID_END),
72 SET_FMAN_ICID_ENTRY(0x09, FSL_DPAA1_STREAM_ID_END),
73 SET_FMAN_ICID_ENTRY(0x0a, FSL_DPAA1_STREAM_ID_END),
74 SET_FMAN_ICID_ENTRY(0x0b, FSL_DPAA1_STREAM_ID_END),
75 SET_FMAN_ICID_ENTRY(0x0c, FSL_DPAA1_STREAM_ID_END),
76 SET_FMAN_ICID_ENTRY(0x0d, FSL_DPAA1_STREAM_ID_END),
77 SET_FMAN_ICID_ENTRY(0x28, FSL_DPAA1_STREAM_ID_END),
78 SET_FMAN_ICID_ENTRY(0x29, FSL_DPAA1_STREAM_ID_END),
79 SET_FMAN_ICID_ENTRY(0x2a, FSL_DPAA1_STREAM_ID_END),
80 SET_FMAN_ICID_ENTRY(0x2b, FSL_DPAA1_STREAM_ID_END),
81 SET_FMAN_ICID_ENTRY(0x2c, FSL_DPAA1_STREAM_ID_END),
82 SET_FMAN_ICID_ENTRY(0x2d, FSL_DPAA1_STREAM_ID_END),
83 SET_FMAN_ICID_ENTRY(0x10, FSL_DPAA1_STREAM_ID_END),
84 SET_FMAN_ICID_ENTRY(0x11, FSL_DPAA1_STREAM_ID_END),
85 SET_FMAN_ICID_ENTRY(0x30, FSL_DPAA1_STREAM_ID_END),
86 SET_FMAN_ICID_ENTRY(0x31, FSL_DPAA1_STREAM_ID_END),
87};
88
89int fman_icid_tbl_sz = ARRAY_SIZE(fman_icid_tbl);
90#endif