blob: 258786b50e364d101b0919f38a08988b1ded912d [file] [log] [blame]
Dirk Behmee0e49fe2008-12-14 09:47:15 +01001/*
2 * (C) Copyright 2008
3 * Texas Instruments, <www.ti.com>
4 *
5 * Author :
6 * Manikandan Pillai <mani.pillai@ti.com>
7 *
8 * Derived from Beagle Board and 3430 SDP code by
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <khasim@ti.com>
11 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +020012 * SPDX-License-Identifier: GPL-2.0+
Dirk Behmee0e49fe2008-12-14 09:47:15 +010013 */
14
15#include <common.h>
16#include <asm/io.h>
17#include <asm/arch/mem.h> /* get mem tables */
18#include <asm/arch/sys_proto.h>
19#include <i2c.h>
Nikita Kiryanov275c05a2012-01-05 02:03:22 +000020#include <linux/compiler.h>
Dirk Behmee0e49fe2008-12-14 09:47:15 +010021
22extern omap3_sysinfo sysinfo;
Dirk Behmedc7af202009-08-08 09:30:21 +020023static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
Sanjeev Premi9659e3f2011-07-18 09:12:24 -040024
25#ifdef CONFIG_DISPLAY_CPUINFO
Sanjeev Premifcbb44f2009-04-27 21:27:54 +053026static char *rev_s[CPU_3XX_MAX_REV] = {
27 "1.0",
28 "2.0",
29 "2.1",
30 "3.0",
Steve Sakomanad74ace2010-08-17 14:39:34 -070031 "3.1",
32 "UNKNOWN",
33 "UNKNOWN",
34 "3.1.2"};
Dirk Behmee0e49fe2008-12-14 09:47:15 +010035
Howard D. Gray3082bc62011-09-04 14:11:17 -040036/* this is the revision table for 37xx CPUs */
37static char *rev_s_37xx[CPU_37XX_MAX_REV] = {
38 "1.0",
39 "1.1",
40 "1.2"};
Sanjeev Premi21614962011-09-23 05:29:45 +000041#endif /* CONFIG_DISPLAY_CPUINFO */
Howard D. Gray3082bc62011-09-04 14:11:17 -040042
Dirk Behme12dbcf62009-03-12 19:30:50 +010043/*****************************************************************
44 * dieid_num_r(void) - read and set die ID
45 *****************************************************************/
46void dieid_num_r(void)
47{
Dirk Behmedc7af202009-08-08 09:30:21 +020048 struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
Dirk Behme12dbcf62009-03-12 19:30:50 +010049 char *uid_s, die_id[34];
50 u32 id[4];
51
52 memset(die_id, 0, sizeof(die_id));
53
54 uid_s = getenv("dieid#");
55
56 if (uid_s == NULL) {
57 id[3] = readl(&id_base->die_id_0);
58 id[2] = readl(&id_base->die_id_1);
59 id[1] = readl(&id_base->die_id_2);
60 id[0] = readl(&id_base->die_id_3);
61 sprintf(die_id, "%08x%08x%08x%08x", id[0], id[1], id[2], id[3]);
62 setenv("dieid#", die_id);
63 uid_s = die_id;
64 }
65
66 printf("Die ID #%s\n", uid_s);
67}
68
Dirk Behmee0e49fe2008-12-14 09:47:15 +010069/******************************************
Dirk Behme2d0d4fa2009-02-12 18:55:42 +010070 * get_cpu_type(void) - extract cpu info
71 ******************************************/
72u32 get_cpu_type(void)
73{
74 return readl(&ctrl_base->ctrl_omap_stat);
75}
76
77/******************************************
Steve Sakomanad74ace2010-08-17 14:39:34 -070078 * get_cpu_id(void) - extract cpu id
79 * returns 0 for ES1.0, cpuid otherwise
Dirk Behmee0e49fe2008-12-14 09:47:15 +010080 ******************************************/
Steve Sakomanad74ace2010-08-17 14:39:34 -070081u32 get_cpu_id(void)
Dirk Behmee0e49fe2008-12-14 09:47:15 +010082{
Dirk Behmedc7af202009-08-08 09:30:21 +020083 struct ctrl_id *id_base;
Steve Sakomanad74ace2010-08-17 14:39:34 -070084 u32 cpuid = 0;
Dirk Behmee0e49fe2008-12-14 09:47:15 +010085
86 /*
87 * On ES1.0 the IDCODE register is not exposed on L4
Sanjeev Premifcbb44f2009-04-27 21:27:54 +053088 * so using CPU ID to differentiate between ES1.0 and > ES1.0.
Dirk Behmee0e49fe2008-12-14 09:47:15 +010089 */
90 __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
Steve Sakomanad74ace2010-08-17 14:39:34 -070091 if ((cpuid & 0xf) == 0x0) {
92 return 0;
93 } else {
Sanjeev Premifcbb44f2009-04-27 21:27:54 +053094 /* Decode the IDs on > ES1.0 */
Dirk Behmedc7af202009-08-08 09:30:21 +020095 id_base = (struct ctrl_id *) OMAP34XX_ID_L4_IO_BASE;
Dirk Behmee0e49fe2008-12-14 09:47:15 +010096
Steve Sakomanad74ace2010-08-17 14:39:34 -070097 cpuid = readl(&id_base->idcode);
98 }
99
100 return cpuid;
101}
102
103/******************************************
104 * get_cpu_family(void) - extract cpu info
105 ******************************************/
106u32 get_cpu_family(void)
107{
108 u16 hawkeye;
109 u32 cpu_family;
110 u32 cpuid = get_cpu_id();
Sanjeev Premifcbb44f2009-04-27 21:27:54 +0530111
Steve Sakomanad74ace2010-08-17 14:39:34 -0700112 if (cpuid == 0)
113 return CPU_OMAP34XX;
Sanjeev Premifcbb44f2009-04-27 21:27:54 +0530114
Steve Sakomanad74ace2010-08-17 14:39:34 -0700115 hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff;
116 switch (hawkeye) {
117 case HAWKEYE_OMAP34XX:
118 cpu_family = CPU_OMAP34XX;
119 break;
120 case HAWKEYE_AM35XX:
121 cpu_family = CPU_AM35XX;
122 break;
123 case HAWKEYE_OMAP36XX:
124 cpu_family = CPU_OMAP36XX;
125 break;
126 default:
127 cpu_family = CPU_OMAP34XX;
Sanjeev Premifcbb44f2009-04-27 21:27:54 +0530128 }
Steve Sakomanad74ace2010-08-17 14:39:34 -0700129
130 return cpu_family;
Dirk Behmee0e49fe2008-12-14 09:47:15 +0100131}
132
Steve Sakomanad74ace2010-08-17 14:39:34 -0700133/******************************************
134 * get_cpu_rev(void) - extract version info
135 ******************************************/
136u32 get_cpu_rev(void)
137{
138 u32 cpuid = get_cpu_id();
139
140 if (cpuid == 0)
141 return CPU_3XX_ES10;
142 else
143 return (cpuid >> CPU_3XX_ID_SHIFT) & 0xf;
144}
145
146/*****************************************************************
147 * get_sku_id(void) - read sku_id to get info on max clock rate
148 *****************************************************************/
149u32 get_sku_id(void)
150{
151 struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
152 return readl(&id_base->sku_id) & SKUID_CLK_MASK;
153}
154
Dirk Behmee0e49fe2008-12-14 09:47:15 +0100155/***************************************************************************
156 * get_gpmc0_base() - Return current address hardware will be
157 * fetching from. The below effectively gives what is correct, its a bit
158 * mis-leading compared to the TRM. For the most general case the mask
159 * needs to be also taken into account this does work in practice.
160 * - for u-boot we currently map:
161 * -- 0 to nothing,
162 * -- 4 to flash
163 * -- 8 to enent
164 * -- c to wifi
165 ****************************************************************************/
166u32 get_gpmc0_base(void)
167{
168 u32 b;
169
Dirk Behmea4becd62009-08-08 09:30:22 +0200170 b = readl(&gpmc_cfg->cs[0].config7);
Dirk Behmee0e49fe2008-12-14 09:47:15 +0100171 b &= 0x1F; /* keep base [5:0] */
172 b = b << 24; /* ret 0x0b000000 */
173 return b;
174}
175
176/*******************************************************************
177 * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
178 *******************************************************************/
179u32 get_gpmc0_width(void)
180{
181 return WIDTH_16BIT;
182}
183
184/*************************************************************************
185 * get_board_rev() - setup to pass kernel board revision information
186 * returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
187 *************************************************************************/
Nikita Kiryanov275c05a2012-01-05 02:03:22 +0000188u32 __weak get_board_rev(void)
Dirk Behmee0e49fe2008-12-14 09:47:15 +0100189{
190 return 0x20;
191}
192
Dirk Behmee0e49fe2008-12-14 09:47:15 +0100193/********************************************************
194 * get_base(); get upper addr of current execution
195 *******************************************************/
196u32 get_base(void)
197{
198 u32 val;
199
200 __asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
201 val &= 0xF0000000;
202 val >>= 28;
203 return val;
204}
205
206/********************************************************
207 * is_running_in_flash() - tell if currently running in
208 * FLASH.
209 *******************************************************/
210u32 is_running_in_flash(void)
211{
212 if (get_base() < 4)
213 return 1; /* in FLASH */
214
215 return 0; /* running in SRAM or SDRAM */
216}
217
218/********************************************************
219 * is_running_in_sram() - tell if currently running in
220 * SRAM.
221 *******************************************************/
222u32 is_running_in_sram(void)
223{
224 if (get_base() == 4)
225 return 1; /* in SRAM */
226
227 return 0; /* running in FLASH or SDRAM */
228}
229
230/********************************************************
231 * is_running_in_sdram() - tell if currently running in
232 * SDRAM.
233 *******************************************************/
234u32 is_running_in_sdram(void)
235{
236 if (get_base() > 4)
237 return 1; /* in SDRAM */
238
239 return 0; /* running in SRAM or FLASH */
240}
241
242/***************************************************************
243 * get_boot_type() - Is this an XIP type device or a stream one
244 * bits 4-0 specify type. Bit 5 says mem/perif
245 ***************************************************************/
246u32 get_boot_type(void)
247{
248 return (readl(&ctrl_base->status) & SYSBOOT_MASK);
249}
250
251/*************************************************************
252 * get_device_type(): tell if GP/HS/EMU/TST
253 *************************************************************/
254u32 get_device_type(void)
255{
256 return ((readl(&ctrl_base->status) & (DEVICE_MASK)) >> 8);
257}
Sanjeev Premie32ef2e2009-04-27 21:27:27 +0530258
259#ifdef CONFIG_DISPLAY_CPUINFO
260/**
261 * Print CPU information
262 */
263int print_cpuinfo (void)
264{
Steve Sakomanad74ace2010-08-17 14:39:34 -0700265 char *cpu_family_s, *cpu_s, *sec_s, *max_clk;
Sanjeev Premie32ef2e2009-04-27 21:27:27 +0530266
Steve Sakomanad74ace2010-08-17 14:39:34 -0700267 switch (get_cpu_family()) {
268 case CPU_OMAP34XX:
269 cpu_family_s = "OMAP";
270 switch (get_cpu_type()) {
271 case OMAP3503:
272 cpu_s = "3503";
273 break;
274 case OMAP3515:
275 cpu_s = "3515";
276 break;
277 case OMAP3525:
278 cpu_s = "3525";
279 break;
280 case OMAP3530:
281 cpu_s = "3530";
282 break;
283 default:
284 cpu_s = "35XX";
285 break;
286 }
287 if ((get_cpu_rev() >= CPU_3XX_ES31) &&
288 (get_sku_id() == SKUID_CLK_720MHZ))
man.huber@arcor.deb709cd12013-04-10 12:12:17 +0000289 max_clk = "720 MHz";
Steve Sakomanad74ace2010-08-17 14:39:34 -0700290 else
man.huber@arcor.deb709cd12013-04-10 12:12:17 +0000291 max_clk = "600 MHz";
Steve Sakomanad74ace2010-08-17 14:39:34 -0700292
Sanjeev Premie32ef2e2009-04-27 21:27:27 +0530293 break;
Steve Sakomanad74ace2010-08-17 14:39:34 -0700294 case CPU_AM35XX:
295 cpu_family_s = "AM";
296 switch (get_cpu_type()) {
297 case AM3505:
298 cpu_s = "3505";
299 break;
300 case AM3517:
301 cpu_s = "3517";
302 break;
303 default:
304 cpu_s = "35XX";
305 break;
306 }
307 max_clk = "600 Mhz";
Sanjeev Premie32ef2e2009-04-27 21:27:27 +0530308 break;
Steve Sakomanad74ace2010-08-17 14:39:34 -0700309 case CPU_OMAP36XX:
310 cpu_family_s = "OMAP";
311 switch (get_cpu_type()) {
312 case OMAP3730:
313 cpu_s = "3630/3730";
314 break;
315 default:
316 cpu_s = "36XX/37XX";
317 break;
318 }
319 max_clk = "1 Ghz";
Sanjeev Premie32ef2e2009-04-27 21:27:27 +0530320 break;
321 default:
Steve Sakomanad74ace2010-08-17 14:39:34 -0700322 cpu_family_s = "OMAP";
Sanjeev Premie32ef2e2009-04-27 21:27:27 +0530323 cpu_s = "35XX";
Steve Sakomanad74ace2010-08-17 14:39:34 -0700324 max_clk = "600 Mhz";
Sanjeev Premie32ef2e2009-04-27 21:27:27 +0530325 }
326
327 switch (get_device_type()) {
328 case TST_DEVICE:
329 sec_s = "TST";
330 break;
331 case EMU_DEVICE:
332 sec_s = "EMU";
333 break;
334 case HS_DEVICE:
335 sec_s = "HS";
336 break;
337 case GP_DEVICE:
338 sec_s = "GP";
339 break;
340 default:
341 sec_s = "?";
342 }
343
Howard D. Gray3082bc62011-09-04 14:11:17 -0400344 if (CPU_OMAP36XX == get_cpu_family())
Andreas Bießmann4738e362013-07-08 15:21:34 +0200345 printf("%s%s-%s ES%s, CPU-OPP2, L3-200MHz, Max CPU Clock %s\n",
346 cpu_family_s, cpu_s, sec_s,
347 rev_s_37xx[get_cpu_rev()], max_clk);
Howard D. Gray3082bc62011-09-04 14:11:17 -0400348 else
349 printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n",
Steve Sakomanad74ace2010-08-17 14:39:34 -0700350 cpu_family_s, cpu_s, sec_s,
351 rev_s[get_cpu_rev()], max_clk);
Sanjeev Premie32ef2e2009-04-27 21:27:27 +0530352
353 return 0;
354}
355#endif /* CONFIG_DISPLAY_CPUINFO */