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git01.mediatek.com / filogic / uboot / 471e0ec5bfa70376cf42d7896485f13d3f127d13 / . / board / evb4510 / lowlevel_init.S
blob: 7184d7259a5c30981999d011016c2ba7316000b3 [file] [log] [blame]
wdenkf2140d52004-07-01 16:30:44 +0000[diff] [blame]1/*
2 * Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
3 * Curt Brune <curt@cucy.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24
25#include <config.h>
26#include <version.h>
27#include <asm/hardware.h>
28
29/***********************************************************************
30 * Configure Memory Map
31 *
32 * This memory map allows us to relocate from FLASH to SRAM. After
33 * power-on reset the CPU only knows about the FLASH memory at address
wdenk336b2bc2005-04-02 23:52:25 +0000[diff] [blame]34 * 0x00000000. After lowlevel_init completes the memory map will be:
wdenkf2140d52004-07-01 16:30:44 +0000[diff] [blame]35 *
36 * Memory Addr
37 * 0x00000000
38 * to 8MB SRAM (U5) -- 8MB Map
39 * 0x00800000
40 *
41 * 0x01000000
42 * to 2MB Flash @ 0x00000000 (U7) -- 2MB Map
43 * 0x01200000
44 *
45 * 0x02000000
46 * to 512KB Flash @ 0x02000000 (U9) -- 2MB Map
47 * 0x02080000
48 *
49 * Load all 12 memory registers with the STMIA instruction since
50 * memory access is disabled once these registers are written. The
51 * last register written re-enables memory access. For more info see
52 * the user's manual for the S3C4510B, available from Samsung's web
53 * site. Search for part number "S3C4510B".
54 *
55 ***********************************************************************/
56
wdenk336b2bc2005-04-02 23:52:25 +0000[diff] [blame]57.globl lowlevel_init
58lowlevel_init:
wdenkf2140d52004-07-01 16:30:44 +0000[diff] [blame]59
60 /* preserve the temp register (r12 AKA ip) and remap it. */
61 ldr r1, =SRAM_BASE+0xC
62 add r0, r12, #0x01000000
63 str r0, [r1]
64
65 /* remap the link register for when we return */
66 add lr, lr, #0x01000000
67
68 /* store a short program in the on chip SRAM, which is
69 * unaffected when remapping memory. Note the cache must be
70 * disabled for the on chip SRAM to be available.
71 */
72 ldr r1, =SRAM_BASE
73 ldr r0, =0xe8801ffe /* stmia r0, {r1-r12} */
74 str r0, [r1]
75 add r1, r1, #4
76 ldr r0, =0xe59fc000 /* ldr r12, [pc, #0] */
77 str r0, [r1]
78 add r1, r1, #4
79 ldr r0, =0xe1a0f00e /* mov pc, lr */
80 str r0, [r1]
81
82 adr r0, memory_map_data
83 ldmia r0, {r1-r12}
84 ldr r0, =REG_EXTDBWTH
85
86 ldr pc, =SRAM_BASE
87
88.globl reset_cpu
89reset_cpu:
90 /*
91 * reset the cpu by re-mapping FLASH 0 to 0x0 and jumping to
92 * address 0x0. We accomplish this by storing a few
93 * instructions into the on chip SRAM (8KB) and run from
94 * there. Note the cache must be disabled for the on chip
95 * SRAM to be available.
96 *
97 * load r2 with REG_ROMCON0
98 * load r3 with 0x12040060 configure FLASH bank 0 @ 0x00000000
99 * load r4 with REG_DRAMCON0
100 * load r5 with 0x08000380 configure RAM bank 0 @ 0x01000000
101 * load r6 with REG_REFEXTCON
102 * load r7 with 0x9c218360
103 * load r8 with 0x0
104 * store str r3,[r2] @ SRAM_BASE
105 * store str r5,[r4] @ SRAM_BASE + 0x4
106 * store str r7,[r6] @ SRAM_BASE + 0x8
107 * store mov pc,r8 @ SRAM_BASE + 0xC
108 * mov pc, SRAM_BASE
109 *
110 */
111
112 /* disable cache */
113 ldr r0, =REG_SYSCFG
114 ldr r1, =0x83ffffa0 /* cache-disabled */
115 str r1, [r0]
116
117 ldr r2, =REG_ROMCON0
118 ldr r3, =0x02000060 /* Bank0 2MB FLASH @ 0x00000000 */
119 ldr r4, =REG_DRAMCON0
120 ldr r5, =0x18040380 /* DRAM0 8MB SRAM @ 0x01000000 */
121 ldr r6, =REG_REFEXTCON
122 ldr r7, =0xce278360
123 ldr r8, =0x00000000
124 ldr r1, =SRAM_BASE
125 ldr r0, =0xe5823000 /* str r3, [r2] */
126 str r0, [r1]
127 ldr r1, =SRAM_BASE+4
128 ldr r0, =0xe5845000 /* str r5, [r4] */
129 str r0, [r1]
130 ldr r1, =SRAM_BASE+8
131 ldr r0, =0xe5867000 /* str r7, [r6] */
132 str r0, [r1]
133 ldr r1, =SRAM_BASE+0xC
134 ldr r0, =0xe1a0f008 /* mov pc, r8 */
135 str r0, [r1]
136 ldr r1, =SRAM_BASE
137 mov pc, r1
138
139 /* never return */
140
141/************************************************************************
142 * Below are twelve 32-bit values for the twelve memory registers of
143 * the system manager, starting with register REG_EXTDBWTH.
144 ***********************************************************************/
145memory_map_data:
146 .long 0x00f03005 /* memory widths */
147 .long 0x12040060 /* Bank0 2MB FLASH @ 0x01000000 */
148 .long 0x22080060 /* Bank1 512KB FLASH @ 0x02000000 */
149 .long 0x00000000
150 .long 0x00000000
151 .long 0x00000000
152 .long 0x00000000
153 .long 0x08000380 /* DRAM0 8MB SRAM @ 0x00000000 */
154 .long 0x00000000
155 .long 0x00000000
156 .long 0x00000000
157 .long 0x9c218360 /* enable memory */