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git01.mediatek.com / filogic / uboot / 4703ea686b466b779524b47868fbf5734f57eb00 / . / board / renesas / sh7757lcr / lowlevel_init.S
blob: 6db26d9450dd0785d87d06caec65edd4cba70f6f [file] [log] [blame]
Yoshihiro Shimodaa7d382c2011-02-02 10:05:36 +0900[diff] [blame]1/*
2 * Copyright (C) 2011 Renesas Solutions Corp.
3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]4 * SPDX-License-Identifier: GPL-2.0+
Yoshihiro Shimodaa7d382c2011-02-02 10:05:36 +0900[diff] [blame]5 */
6
7#include <config.h>
Yoshihiro Shimodaa7d382c2011-02-02 10:05:36 +0900[diff] [blame]8#include <asm/processor.h>
9#include <asm/macro.h>
10
11.macro or32, addr, data
12 mov.l \addr, r1
13 mov.l \data, r0
14 mov.l @r1, r2
15 or r2, r0
16 mov.l r0, @r1
17.endm
18
19.macro wait_DBCMD
20 mov.l DBWAIT_A, r0
21 mov.l @r0, r1
22.endm
23
24 .global lowlevel_init
25 .section .spiboot1.text
26 .align 2
27
28lowlevel_init:
29
30 /*------- GPIO -------*/
31 write8 PGDR_A, PGDR_D /* eMMC power off */
32
33 write16 PACR_A, PACR_D
34 write16 PBCR_A, PBCR_D
35 write16 PCCR_A, PCCR_D
36 write16 PDCR_A, PDCR_D
37 write16 PECR_A, PECR_D
38 write16 PFCR_A, PFCR_D
39 write16 PGCR_A, PGCR_D
40 write16 PHCR_A, PHCR_D
41 write16 PICR_A, PICR_D
42 write16 PJCR_A, PJCR_D
43 write16 PKCR_A, PKCR_D
44 write16 PLCR_A, PLCR_D
45 write16 PMCR_A, PMCR_D
46 write16 PNCR_A, PNCR_D
47 write16 POCR_A, POCR_D
48 write16 PQCR_A, PQCR_D
49 write16 PRCR_A, PRCR_D
50 write16 PSCR_A, PSCR_D
51 write16 PTCR_A, PTCR_D
52 write16 PUCR_A, PUCR_D
53 write16 PVCR_A, PVCR_D
54 write16 PWCR_A, PWCR_D
55 write16 PXCR_A, PXCR_D
56 write16 PYCR_A, PYCR_D
57 write16 PZCR_A, PZCR_D
58 write16 PSEL0_A, PSEL0_D
59 write16 PSEL1_A, PSEL1_D
60 write16 PSEL2_A, PSEL2_D
61 write16 PSEL3_A, PSEL3_D
62 write16 PSEL4_A, PSEL4_D
63 write16 PSEL5_A, PSEL5_D
64 write16 PSEL6_A, PSEL6_D
65 write16 PSEL7_A, PSEL7_D
66 write16 PSEL8_A, PSEL8_D
67
68 bra exit_gpio
69 nop
70
71 .align 4
72
73/*------- GPIO -------*/
74PGDR_A: .long 0xffec0040
75PACR_A: .long 0xffec0000
76PBCR_A: .long 0xffec0002
77PCCR_A: .long 0xffec0004
78PDCR_A: .long 0xffec0006
79PECR_A: .long 0xffec0008
80PFCR_A: .long 0xffec000a
81PGCR_A: .long 0xffec000c
82PHCR_A: .long 0xffec000e
83PICR_A: .long 0xffec0010
84PJCR_A: .long 0xffec0012
85PKCR_A: .long 0xffec0014
86PLCR_A: .long 0xffec0016
87PMCR_A: .long 0xffec0018
88PNCR_A: .long 0xffec001a
89POCR_A: .long 0xffec001c
90PQCR_A: .long 0xffec0020
91PRCR_A: .long 0xffec0022
92PSCR_A: .long 0xffec0024
93PTCR_A: .long 0xffec0026
94PUCR_A: .long 0xffec0028
95PVCR_A: .long 0xffec002a
96PWCR_A: .long 0xffec002c
97PXCR_A: .long 0xffec002e
98PYCR_A: .long 0xffec0030
99PZCR_A: .long 0xffec0032
100PSEL0_A: .long 0xffec0070
101PSEL1_A: .long 0xffec0072
102PSEL2_A: .long 0xffec0074
103PSEL3_A: .long 0xffec0076
104PSEL4_A: .long 0xffec0078
105PSEL5_A: .long 0xffec007a
106PSEL6_A: .long 0xffec007c
107PSEL7_A: .long 0xffec0082
108PSEL8_A: .long 0xffec0084
109
110PGDR_D: .long 0x80
111PACR_D: .long 0x0000
112PBCR_D: .long 0x0001
113PCCR_D: .long 0x0000
114PDCR_D: .long 0x0000
115PECR_D: .long 0x0000
116PFCR_D: .long 0x0000
117PGCR_D: .long 0x0000
118PHCR_D: .long 0x0000
119PICR_D: .long 0x0000
120PJCR_D: .long 0x0000
121PKCR_D: .long 0x0003
122PLCR_D: .long 0x0000
123PMCR_D: .long 0x0000
124PNCR_D: .long 0x0000
125POCR_D: .long 0x0000
126PQCR_D: .long 0xc000
127PRCR_D: .long 0x0000
128PSCR_D: .long 0x0000
129PTCR_D: .long 0x0000
130#if defined(CONFIG_SH7757_OFFSET_SPI)
131PUCR_D: .long 0x0055
132#else
133PUCR_D: .long 0x0000
134#endif
135PVCR_D: .long 0x0000
136PWCR_D: .long 0x0000
137PXCR_D: .long 0x0000
138PYCR_D: .long 0x0000
139PZCR_D: .long 0x0000
140PSEL0_D: .long 0xfe00
141PSEL1_D: .long 0x0000
142PSEL2_D: .long 0x3000
143PSEL3_D: .long 0xff00
144PSEL4_D: .long 0x771f
145PSEL5_D: .long 0x0ffc
146PSEL6_D: .long 0x00ff
147PSEL7_D: .long 0xfc00
148PSEL8_D: .long 0x0000
149
150 .align 2
151
152exit_gpio:
153 mov #0, r14
154 mova 2f, r0
155 mov.l PC_MASK, r1
156 tst r0, r1
157 bf 2f
158
159 bra exit_pmb
160 nop
161
162 .align 2
163
164/* If CPU runs on SDRAM, PC is 0x8???????. */
165PC_MASK: .long 0x20000000
166
1672:
168 mov #1, r14
169
170 mov.l EXPEVT_A, r0
171 mov.l @r0, r0
172 mov.l EXPEVT_POWER_ON_RESET, r1
173 cmp/eq r0, r1
174 bt 1f
175
176 /*
177 * If EXPEVT value is manual reset or tlb multipul-hit,
178 * initialization of DDR3IF is not necessary.
179 */
180 bra exit_ddr
181 nop
182
1831:
184 /* For Core Reset */
185 mov.l DBACEN_A, r0
186 mov.l @r0, r0
187 cmp/eq #0, r0
188 bt 3f
189
190 /*
191 * If DBACEN == 1(DBSC was already enabled), we have to avoid the
192 * initialization of DDR3-SDRAM.
193 */
194 bra exit_ddr
195 nop
196
1973:
198 /*------- DDR3IF -------*/
199 /* oscillation stabilization time */
200 wait_timer WAIT_OSC_TIME
201
202 /* step 3 */
203 write32 DBCMD_A, DBCMD_RSTL_VAL
204 wait_timer WAIT_30US
205
206 /* step 4 */
207 write32 DBCMD_A, DBCMD_PDEN_VAL
208
209 /* step 5 */
210 write32 DBKIND_A, DBKIND_D
211
212 /* step 6 */
213 write32 DBCONF_A, DBCONF_D
214 write32 DBTR0_A, DBTR0_D
215 write32 DBTR1_A, DBTR1_D
216 write32 DBTR2_A, DBTR2_D
217 write32 DBTR3_A, DBTR3_D
218 write32 DBTR4_A, DBTR4_D
219 write32 DBTR5_A, DBTR5_D
220 write32 DBTR6_A, DBTR6_D
221 write32 DBTR7_A, DBTR7_D
222 write32 DBTR8_A, DBTR8_D
223 write32 DBTR9_A, DBTR9_D
224 write32 DBTR10_A, DBTR10_D
225 write32 DBTR11_A, DBTR11_D
226 write32 DBTR12_A, DBTR12_D
227 write32 DBTR13_A, DBTR13_D
228 write32 DBTR14_A, DBTR14_D
229 write32 DBTR15_A, DBTR15_D
230 write32 DBTR16_A, DBTR16_D
231 write32 DBTR17_A, DBTR17_D
232 write32 DBTR18_A, DBTR18_D
233 write32 DBTR19_A, DBTR19_D
234 write32 DBRNK0_A, DBRNK0_D
235
236 /* step 7 */
237 write32 DBPDCNT3_A, DBPDCNT3_D
238
239 /* step 8 */
240 write32 DBPDCNT1_A, DBPDCNT1_D
241 write32 DBPDCNT2_A, DBPDCNT2_D
242 write32 DBPDLCK_A, DBPDLCK_D
243 write32 DBPDRGA_A, DBPDRGA_D
244 write32 DBPDRGD_A, DBPDRGD_D
245
246 /* step 9 */
247 wait_timer WAIT_30US
248
249 /* step 10 */
250 write32 DBPDCNT0_A, DBPDCNT0_D
251
252 /* step 11 */
253 wait_timer WAIT_30US
254 wait_timer WAIT_30US
255
256 /* step 12 */
257 write32 DBCMD_A, DBCMD_WAIT_VAL
258 wait_DBCMD
259
260 /* step 13 */
261 write32 DBCMD_A, DBCMD_RSTH_VAL
262 wait_DBCMD
263
264 /* step 14 */
265 write32 DBCMD_A, DBCMD_WAIT_VAL
266 write32 DBCMD_A, DBCMD_WAIT_VAL
267 write32 DBCMD_A, DBCMD_WAIT_VAL
268 write32 DBCMD_A, DBCMD_WAIT_VAL
269
270 /* step 15 */
271 write32 DBCMD_A, DBCMD_PDXT_VAL
272
273 /* step 16 */
274 write32 DBCMD_A, DBCMD_MRS2_VAL
275
276 /* step 17 */
277 write32 DBCMD_A, DBCMD_MRS3_VAL
278
279 /* step 18 */
280 write32 DBCMD_A, DBCMD_MRS1_VAL
281
282 /* step 19 */
283 write32 DBCMD_A, DBCMD_MRS0_VAL
284
285 /* step 20 */
286 write32 DBCMD_A, DBCMD_ZQCL_VAL
287
288 write32 DBCMD_A, DBCMD_REF_VAL
289 write32 DBCMD_A, DBCMD_REF_VAL
290 wait_DBCMD
291
292 /* step 21 */
293 write32 DBADJ0_A, DBADJ0_D
294 write32 DBADJ1_A, DBADJ1_D
295 write32 DBADJ2_A, DBADJ2_D
296
297 /* step 22 */
298 write32 DBRFCNF0_A, DBRFCNF0_D
299 write32 DBRFCNF1_A, DBRFCNF1_D
300 write32 DBRFCNF2_A, DBRFCNF2_D
301
302 /* step 23 */
303 write32 DBCALCNF_A, DBCALCNF_D
304
305 /* step 24 */
306 write32 DBRFEN_A, DBRFEN_D
307 write32 DBCMD_A, DBCMD_SRXT_VAL
308
309 /* step 25 */
310 write32 DBACEN_A, DBACEN_D
311
312 /* step 26 */
313 wait_DBCMD
314
Nobuhiro Iwamatsu67395912011-10-31 13:16:02 +0900[diff] [blame]315#if defined(CONFIG_SH7757LCR_DDR_ECC)
Yoshihiro Shimodaa7d382c2011-02-02 10:05:36 +0900[diff] [blame]316 /* enable DDR-ECC */
317 write32 ECD_ECDEN_A, ECD_ECDEN_D
318 write32 ECD_INTSR_A, ECD_INTSR_D
319 write32 ECD_SPACER_A, ECD_SPACER_D
320 write32 ECD_MCR_A, ECD_MCR_D
Nobuhiro Iwamatsu67395912011-10-31 13:16:02 +0900[diff] [blame]321#endif
Yoshihiro Shimodaa7d382c2011-02-02 10:05:36 +0900[diff] [blame]322 bra exit_ddr
323 nop
324
325 .align 4
326
327EXPEVT_A: .long 0xff000024
328EXPEVT_POWER_ON_RESET: .long 0x00000000
329
330/*------- DDR3IF -------*/
331DBCMD_A: .long 0xfe800018
332DBKIND_A: .long 0xfe800020
333DBCONF_A: .long 0xfe800024
334DBTR0_A: .long 0xfe800040
335DBTR1_A: .long 0xfe800044
336DBTR2_A: .long 0xfe800048
337DBTR3_A: .long 0xfe800050
338DBTR4_A: .long 0xfe800054
339DBTR5_A: .long 0xfe800058
340DBTR6_A: .long 0xfe80005c
341DBTR7_A: .long 0xfe800060
342DBTR8_A: .long 0xfe800064
343DBTR9_A: .long 0xfe800068
344DBTR10_A: .long 0xfe80006c
345DBTR11_A: .long 0xfe800070
346DBTR12_A: .long 0xfe800074
347DBTR13_A: .long 0xfe800078
348DBTR14_A: .long 0xfe80007c
349DBTR15_A: .long 0xfe800080
350DBTR16_A: .long 0xfe800084
351DBTR17_A: .long 0xfe800088
352DBTR18_A: .long 0xfe80008c
353DBTR19_A: .long 0xfe800090
354DBRNK0_A: .long 0xfe800100
355DBPDCNT0_A: .long 0xfe800200
356DBPDCNT1_A: .long 0xfe800204
357DBPDCNT2_A: .long 0xfe800208
358DBPDCNT3_A: .long 0xfe80020c
359DBPDLCK_A: .long 0xfe800280
360DBPDRGA_A: .long 0xfe800290
361DBPDRGD_A: .long 0xfe8002a0
362DBADJ0_A: .long 0xfe8000c0
363DBADJ1_A: .long 0xfe8000c4
364DBADJ2_A: .long 0xfe8000c8
365DBRFCNF0_A: .long 0xfe8000e0
366DBRFCNF1_A: .long 0xfe8000e4
367DBRFCNF2_A: .long 0xfe8000e8
368DBCALCNF_A: .long 0xfe8000f4
369DBRFEN_A: .long 0xfe800014
370DBACEN_A: .long 0xfe800010
371DBWAIT_A: .long 0xfe80001c
372
373WAIT_OSC_TIME: .long 6000
374WAIT_30US: .long 13333
375
376DBCMD_RSTL_VAL: .long 0x20000000
377DBCMD_PDEN_VAL: .long 0x1000d73c
378DBCMD_WAIT_VAL: .long 0x0000d73c
379DBCMD_RSTH_VAL: .long 0x2100d73c
380DBCMD_PDXT_VAL: .long 0x110000c8
381DBCMD_MRS0_VAL: .long 0x28000930
382DBCMD_MRS1_VAL: .long 0x29000004
383DBCMD_MRS2_VAL: .long 0x2a000008
384DBCMD_MRS3_VAL: .long 0x2b000000
385DBCMD_ZQCL_VAL: .long 0x03000200
386DBCMD_REF_VAL: .long 0x0c000000
387DBCMD_SRXT_VAL: .long 0x19000000
388DBKIND_D: .long 0x00000007
389DBCONF_D: .long 0x0f030a01
390DBTR0_D: .long 0x00000007
391DBTR1_D: .long 0x00000006
392DBTR2_D: .long 0x00000000
393DBTR3_D: .long 0x00000007
394DBTR4_D: .long 0x00070007
395DBTR5_D: .long 0x0000001b
396DBTR6_D: .long 0x00000014
397DBTR7_D: .long 0x00000005
398DBTR8_D: .long 0x00000015
399DBTR9_D: .long 0x00000006
400DBTR10_D: .long 0x00000008
401DBTR11_D: .long 0x00000007
402DBTR12_D: .long 0x0000000e
403DBTR13_D: .long 0x00000056
404DBTR14_D: .long 0x00000006
405DBTR15_D: .long 0x00000004
406DBTR16_D: .long 0x00150002
407DBTR17_D: .long 0x000c0017
408DBTR18_D: .long 0x00000200
409DBTR19_D: .long 0x00000040
410DBRNK0_D: .long 0x00000001
411DBPDCNT0_D: .long 0x00000001
412DBPDCNT1_D: .long 0x00000001
413DBPDCNT2_D: .long 0x00000000
414DBPDCNT3_D: .long 0x00004010
415DBPDLCK_D: .long 0x0000a55a
416DBPDRGA_D: .long 0x00000028
417DBPDRGD_D: .long 0x00017100
418
419DBADJ0_D: .long 0x00000000
420DBADJ1_D: .long 0x00000000
421DBADJ2_D: .long 0x18061806
422DBRFCNF0_D: .long 0x000001ff
423DBRFCNF1_D: .long 0x08001000
424DBRFCNF2_D: .long 0x00000000
425DBCALCNF_D: .long 0x0000ffff
426DBRFEN_D: .long 0x00000001
427DBACEN_D: .long 0x00000001
428
429/*------- DDR-ECC -------*/
430ECD_ECDEN_A: .long 0xffc1012c
431ECD_ECDEN_D: .long 0x00000001
432ECD_INTSR_A: .long 0xfe900024
433ECD_INTSR_D: .long 0xffffffff
434ECD_SPACER_A: .long 0xfe900018
435ECD_SPACER_D: .long SH7757LCR_SDRAM_ECC_SETTING
436ECD_MCR_A: .long 0xfe900010
437ECD_MCR_D: .long 0x00000001
438
439 .align 2
440exit_ddr:
441
442#if defined(CONFIG_SH_32BIT)
443 /*------- set PMB -------*/
444 write32 PASCR_A, PASCR_29BIT_D
445 write32 MMUCR_A, MMUCR_D
446
447 /*****************************************************************
448 * ent virt phys v sz c wt
449 * 0 0xa0000000 0x00000000 1 128M 0 1
450 * 1 0xa8000000 0x48000000 1 128M 0 1
451 * 5 0x88000000 0x48000000 1 128M 1 1
452 */
453 write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D
454 write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D
455 write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D
456 write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D
457 write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D
458 write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D
459
460 write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D
461 write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D
462 write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D
463 write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D
464 write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D
465 write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D
466 write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D
467 write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D
468 write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D
469 write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D
470 write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D
471 write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D
472 write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D
473
474 write32 PASCR_A, PASCR_INIT
475 mov.l DUMMY_ADDR, r0
476 icbi @r0
477#endif /* if defined(CONFIG_SH_32BIT) */
478
479exit_pmb:
480 /* CPU is running on ILRAM? */
481 mov r14, r0
482 tst #1, r0
483 bt 1f
484
485 mov.l _bss_start, r15
486 mov.l _spiboot_main, r0
487100: bsrf r0
488 nop
489
490 .align 2
491_spiboot_main: .long (spiboot_main - (100b + 4))
492_bss_start: .long bss_start
493
4941:
495
496 write32 CCR_A, CCR_D
497
498 rts
499 nop
500
501 .align 4
502
503#if defined(CONFIG_SH_32BIT)
504/*------- set PMB -------*/
505PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0)
506PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1)
507PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5)
508PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2)
509PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3)
510PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4)
511PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6)
512PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7)
513PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8)
514PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9)
515PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10)
516PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11)
517PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12)
518PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13)
519PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14)
520PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15)
521
522PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0)
523PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88)
524PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8)
525PMB_ADDR_NOT_USE_D: .long 0x00000000
526
527PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0)
528PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1)
529PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5)
530
531/* ppn ub v s1 s0 c wt */
532PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
533PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
534PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
535
536PASCR_A: .long 0xff000070
537DUMMY_ADDR: .long 0xa0000000
538PASCR_29BIT_D: .long 0x00000000
539PASCR_INIT: .long 0x80000080
540MMUCR_A: .long 0xff000010
541MMUCR_D: .long 0x00000004 /* clear ITLB */
542#endif /* CONFIG_SH_32BIT */
543
544CCR_A: .long CCR
545CCR_D: .long CCR_CACHE_INIT