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git01.mediatek.com / filogic / uboot / 46c1d9fb41d812ab2f173f716fff628a0cfd1ae0 / . / arch / sandbox / dts / test.dts
blob: 366826333181b96d1186ab0a7be8b5a6b1fde662 [file] [log] [blame]
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]1/dts-v1/;
2
3/ {
4 model = "sandbox";
5 compatible = "sandbox";
6 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]7 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]8
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]9 aliases {
10 console = &uart0;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]11 eth0 = "/eth@10002000";
Bin Meng04a11cb2015-08-27 22:25:53 -0700[diff] [blame]12 eth3 = &eth_3;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]13 eth5 = &eth_5;
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]14 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -0600[diff] [blame]15 mmc0 = "/mmc0";
16 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]17 pci0 = &pci0;
18 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -0700[diff] [blame]19 pci2 = &pci2;
Nishanth Menonedf85812015-09-17 15:42:41 -0500[diff] [blame]20 remoteproc1 = &rproc_1;
21 remoteproc2 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]22 rtc0 = &rtc_0;
23 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]24 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +0200[diff] [blame]25 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]26 testbus3 = "/some-bus";
27 testfdt0 = "/some-bus/c-test@0";
28 testfdt1 = "/some-bus/c-test@1";
29 testfdt3 = "/b-test";
30 testfdt5 = "/some-bus/c-test@5";
31 testfdt8 = "/a-test";
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +0200[diff] [blame]32 fdt-dummy0 = "/translation-test@8000/dev@0,0";
33 fdt-dummy1 = "/translation-test@8000/dev@1,100";
34 fdt-dummy2 = "/translation-test@8000/dev@2,200";
35 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]36 usb0 = &usb_0;
37 usb1 = &usb_1;
38 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +0200[diff] [blame]39 axi0 = &axi;
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]40 };
41
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]42 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]43 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]44 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]45 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]46 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]47 u-boot,dm-pre-reloc;
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]48 test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>,
49 <0>, <&gpio_a 12>;
50 test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>,
51 <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>,
52 <&gpio_b 9 0xc 3 2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]53 };
54
55 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]56 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]57 compatible = "not,compatible";
58 };
59
60 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]61 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]62 };
63
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200[diff] [blame]64 bind-test {
65 bind-test-child1 {
66 compatible = "sandbox,phy";
67 #phy-cells = <1>;
68 };
69
70 bind-test-child2 {
71 compatible = "simple-bus";
72 };
73 };
74
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]75 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]76 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]77 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]78 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]79 ping-add = <3>;
80 };
81
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200[diff] [blame]82 phy_provider0: gen_phy@0 {
83 compatible = "sandbox,phy";
84 #phy-cells = <1>;
85 };
86
87 phy_provider1: gen_phy@1 {
88 compatible = "sandbox,phy";
89 #phy-cells = <0>;
90 broken;
91 };
92
93 gen_phy_user: gen_phy_user {
94 compatible = "simple-bus";
95 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
96 phy-names = "phy1", "phy2", "phy3";
97 };
98
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]99 some-bus {
100 #address-cells = <1>;
101 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]102 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]103 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]104 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]105 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]106 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]107 compatible = "denx,u-boot-fdt-test";
108 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]109 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]110 ping-add = <5>;
111 };
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]112 c-test@0 {
113 compatible = "denx,u-boot-fdt-test";
114 reg = <0>;
115 ping-expect = <6>;
116 ping-add = <6>;
117 };
118 c-test@1 {
119 compatible = "denx,u-boot-fdt-test";
120 reg = <1>;
121 ping-expect = <7>;
122 ping-add = <7>;
123 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]124 };
125
126 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]127 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600[diff] [blame]128 ping-expect = <6>;
129 ping-add = <6>;
130 compatible = "google,another-fdt-test";
131 };
132
133 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]134 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]135 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]136 ping-add = <6>;
137 compatible = "google,another-fdt-test";
138 };
139
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]140 f-test {
141 compatible = "denx,u-boot-fdt-test";
142 };
143
144 g-test {
145 compatible = "denx,u-boot-fdt-test";
146 };
147
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200[diff] [blame]148 clocks {
149 clk_fixed: clk-fixed {
150 compatible = "fixed-clock";
151 #clock-cells = <0>;
152 clock-frequency = <1234>;
153 };
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]154 };
155
156 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]157 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]158 #clock-cells = <1>;
159 };
160
161 clk-test {
162 compatible = "sandbox,clk-test";
163 clocks = <&clk_fixed>,
164 <&clk_sandbox 1>,
165 <&clk_sandbox 0>;
166 clock-names = "fixed", "i2c", "spi";
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]167 };
168
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]169 eth@10002000 {
170 compatible = "sandbox,eth";
171 reg = <0x10002000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]172 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]173 };
174
175 eth_5: eth@10003000 {
176 compatible = "sandbox,eth";
177 reg = <0x10003000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]178 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]179 };
180
Bin Meng04a11cb2015-08-27 22:25:53 -0700[diff] [blame]181 eth_3: sbe5 {
182 compatible = "sandbox,eth";
183 reg = <0x10005000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]184 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng04a11cb2015-08-27 22:25:53 -0700[diff] [blame]185 };
186
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]187 eth@10004000 {
188 compatible = "sandbox,eth";
189 reg = <0x10004000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]190 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]191 };
192
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]193 gpio_a: base-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]194 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]195 gpio-controller;
196 #gpio-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]197 gpio-bank-name = "a";
Simon Glass9e7ab232018-02-03 10:36:59 -0700[diff] [blame]198 sandbox,gpio-count = <20>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]199 };
200
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]201 gpio_b: extra-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]202 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]203 gpio-controller;
204 #gpio-cells = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]205 gpio-bank-name = "b";
Simon Glass9e7ab232018-02-03 10:36:59 -0700[diff] [blame]206 sandbox,gpio-count = <10>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]207 };
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]208
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]209 i2c@0 {
210 #address-cells = <1>;
211 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]212 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]213 compatible = "sandbox,i2c";
214 clock-frequency = <100000>;
215 eeprom@2c {
216 reg = <0x2c>;
217 compatible = "i2c-eeprom";
218 emul {
219 compatible = "sandbox,i2c-eeprom";
220 sandbox,filename = "i2c.bin";
221 sandbox,size = <256>;
222 };
223 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]224
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]225 rtc_0: rtc@43 {
226 reg = <0x43>;
227 compatible = "sandbox-rtc";
228 emul {
229 compatible = "sandbox,i2c-rtc";
230 };
231 };
232
233 rtc_1: rtc@61 {
234 reg = <0x61>;
235 compatible = "sandbox-rtc";
236 emul {
237 compatible = "sandbox,i2c-rtc";
238 };
239 };
240
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]241 sandbox_pmic: sandbox_pmic {
242 reg = <0x40>;
243 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200[diff] [blame]244
245 mc34708: pmic@41 {
246 reg = <0x41>;
247 };
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]248 };
249
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100[diff] [blame]250 adc@0 {
251 compatible = "sandbox,adc";
252 vdd-supply = <&buck2>;
253 vss-microvolts = <0>;
254 };
255
Simon Glass90b6fef2016-01-18 19:52:26 -0700[diff] [blame]256 lcd {
257 u-boot,dm-pre-reloc;
258 compatible = "sandbox,lcd-sdl";
259 xres = <1366>;
260 yres = <768>;
261 };
262
Simon Glassd783eb32015-07-06 12:54:34 -0600[diff] [blame]263 leds {
264 compatible = "gpio-leds";
265
266 iracibble {
267 gpios = <&gpio_a 1 0>;
268 label = "sandbox:red";
269 };
270
271 martinet {
272 gpios = <&gpio_a 2 0>;
273 label = "sandbox:green";
274 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200[diff] [blame]275
276 default_on {
277 gpios = <&gpio_a 5 0>;
278 label = "sandbox:default_on";
279 default-state = "on";
280 };
281
282 default_off {
283 gpios = <&gpio_a 6 0>;
284 label = "sandbox:default_off";
285 default-state = "off";
286 };
Simon Glassd783eb32015-07-06 12:54:34 -0600[diff] [blame]287 };
288
Stephen Warren62f2c902016-05-16 17:41:37 -0600[diff] [blame]289 mbox: mbox {
290 compatible = "sandbox,mbox";
291 #mbox-cells = <1>;
292 };
293
294 mbox-test {
295 compatible = "sandbox,mbox-test";
296 mboxes = <&mbox 100>, <&mbox 1>;
297 mbox-names = "other", "test";
298 };
299
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200[diff] [blame]300 misc-test {
301 compatible = "sandbox,misc_sandbox";
302 };
303
Simon Glasse4fef742017-04-23 20:02:07 -0600[diff] [blame]304 mmc2 {
305 compatible = "sandbox,mmc";
306 };
307
308 mmc1 {
309 compatible = "sandbox,mmc";
310 };
311
312 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600[diff] [blame]313 compatible = "sandbox,mmc";
314 };
315
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]316 pci0: pci-controller0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700[diff] [blame]317 compatible = "sandbox,pci";
318 device_type = "pci";
319 #address-cells = <3>;
320 #size-cells = <2>;
321 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000
322 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700[diff] [blame]323 pci@0,0 {
324 compatible = "pci-generic";
325 reg = <0x0000 0 0 0 0>;
326 emul@0,0 {
327 compatible = "sandbox,swap-case";
328 };
329 };
Simon Glass3a6eae62015-03-05 12:25:34 -0700[diff] [blame]330 pci@1f,0 {
331 compatible = "pci-generic";
332 reg = <0xf800 0 0 0 0>;
333 emul@1f,0 {
334 compatible = "sandbox,swap-case";
335 };
336 };
337 };
338
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]339 pci1: pci-controller1 {
340 compatible = "sandbox,pci";
341 device_type = "pci";
342 #address-cells = <3>;
343 #size-cells = <2>;
344 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
345 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -0700[diff] [blame]346 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
347 0x0c 0x00 0x1234 0x5678>;
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]348 };
349
Bin Meng510dddb2018-08-03 01:14:50 -0700[diff] [blame]350 pci2: pci-controller2 {
351 compatible = "sandbox,pci";
352 device_type = "pci";
353 #address-cells = <3>;
354 #size-cells = <2>;
355 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
356 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
357 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
358 pci@1f,0 {
359 compatible = "pci-generic";
360 reg = <0xf800 0 0 0 0>;
361 emul@1f,0 {
362 compatible = "sandbox,swap-case";
363 };
364 };
365 };
366
Simon Glass9c433fe2017-04-23 20:10:44 -0600[diff] [blame]367 probing {
368 compatible = "simple-bus";
369 test1 {
370 compatible = "denx,u-boot-probe-test";
371 };
372
373 test2 {
374 compatible = "denx,u-boot-probe-test";
375 };
376
377 test3 {
378 compatible = "denx,u-boot-probe-test";
379 };
380
381 test4 {
382 compatible = "denx,u-boot-probe-test";
383 };
384 };
385
Stephen Warren92c67fa2016-07-13 13:45:31 -0600[diff] [blame]386 pwrdom: power-domain {
387 compatible = "sandbox,power-domain";
388 #power-domain-cells = <1>;
389 };
390
391 power-domain-test {
392 compatible = "sandbox,power-domain-test";
393 power-domains = <&pwrdom 2>;
394 };
395
Simon Glasse62f4be2017-04-16 21:01:11 -0600[diff] [blame]396 pwm {
397 compatible = "sandbox,pwm";
398 };
399
400 pwm2 {
401 compatible = "sandbox,pwm";
402 };
403
Simon Glass3d355e62015-07-06 12:54:31 -0600[diff] [blame]404 ram {
405 compatible = "sandbox,ram";
406 };
407
Simon Glassd860f222015-07-06 12:54:29 -0600[diff] [blame]408 reset@0 {
409 compatible = "sandbox,warm-reset";
410 };
411
412 reset@1 {
413 compatible = "sandbox,reset";
414 };
415
Stephen Warren6488e642016-06-17 09:43:59 -0600[diff] [blame]416 resetc: reset-ctl {
417 compatible = "sandbox,reset-ctl";
418 #reset-cells = <1>;
419 };
420
421 reset-ctl-test {
422 compatible = "sandbox,reset-ctl-test";
423 resets = <&resetc 100>, <&resetc 2>;
424 reset-names = "other", "test";
425 };
426
Nishanth Menonedf85812015-09-17 15:42:41 -0500[diff] [blame]427 rproc_1: rproc@1 {
428 compatible = "sandbox,test-processor";
429 remoteproc-name = "remoteproc-test-dev1";
430 };
431
432 rproc_2: rproc@2 {
433 compatible = "sandbox,test-processor";
434 internal-memory-mapped;
435 remoteproc-name = "remoteproc-test-dev2";
436 };
437
Ramon Fried26ed32e2018-07-02 02:57:59 +0300[diff] [blame]438 smem@0 {
439 compatible = "sandbox,smem";
440 };
441
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]442 spi@0 {
443 #address-cells = <1>;
444 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]445 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]446 compatible = "sandbox,spi";
447 cs-gpios = <0>, <&gpio_a 0>;
448 spi.bin@0 {
449 reg = <0>;
450 compatible = "spansion,m25p16", "spi-flash";
451 spi-max-frequency = <40000000>;
452 sandbox,filename = "spi.bin";
453 };
454 };
455
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]456 syscon@0 {
457 compatible = "sandbox,syscon0";
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]458 reg = <0x10 4>;
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]459 };
460
461 syscon@1 {
462 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]463 reg = <0x20 5
464 0x28 6
465 0x30 7
466 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]467 };
468
Masahiro Yamada42ab1072018-04-23 13:26:53 +0900[diff] [blame]469 syscon@2 {
470 compatible = "simple-mfd", "syscon";
471 reg = <0x40 5
472 0x48 6
473 0x50 7
474 0x58 8>;
475 };
476
Thomas Chou6f2cfbf2015-12-11 16:27:34 +0800[diff] [blame]477 timer {
478 compatible = "sandbox,timer";
479 clock-frequency = <1000000>;
480 };
481
Miquel Raynal80938c12018-05-15 11:57:27 +0200[diff] [blame]482 tpm2 {
483 compatible = "sandbox,tpm2";
484 };
485
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]486 uart0: serial {
487 compatible = "sandbox,serial";
488 u-boot,dm-pre-reloc;
Joe Hershberger4c197242015-03-22 17:09:15 -0500[diff] [blame]489 };
490
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]491 usb_0: usb@0 {
492 compatible = "sandbox,usb";
493 status = "disabled";
494 hub {
495 compatible = "sandbox,usb-hub";
496 #address-cells = <1>;
497 #size-cells = <0>;
498 flash-stick {
499 reg = <0>;
500 compatible = "sandbox,usb-flash";
501 };
502 };
503 };
504
505 usb_1: usb@1 {
506 compatible = "sandbox,usb";
507 hub {
508 compatible = "usb-hub";
509 usb,device-class = <9>;
510 hub-emul {
511 compatible = "sandbox,usb-hub";
512 #address-cells = <1>;
513 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -0700[diff] [blame]514 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]515 reg = <0>;
516 compatible = "sandbox,usb-flash";
517 sandbox,filepath = "testflash.bin";
518 };
519
Simon Glass4700fe52015-11-08 23:48:01 -0700[diff] [blame]520 flash-stick@1 {
521 reg = <1>;
522 compatible = "sandbox,usb-flash";
523 sandbox,filepath = "testflash1.bin";
524 };
525
526 flash-stick@2 {
527 reg = <2>;
528 compatible = "sandbox,usb-flash";
529 sandbox,filepath = "testflash2.bin";
530 };
531
Simon Glassc0ccc722015-11-08 23:48:08 -0700[diff] [blame]532 keyb@3 {
533 reg = <3>;
534 compatible = "sandbox,usb-keyb";
535 };
536
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]537 };
538 };
539 };
540
541 usb_2: usb@2 {
542 compatible = "sandbox,usb";
543 status = "disabled";
544 };
545
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200[diff] [blame]546 spmi: spmi@0 {
547 compatible = "sandbox,spmi";
548 #address-cells = <0x1>;
549 #size-cells = <0x1>;
550 pm8916@0 {
551 compatible = "qcom,spmi-pmic";
552 reg = <0x0 0x1>;
553 #address-cells = <0x1>;
554 #size-cells = <0x1>;
555
556 spmi_gpios: gpios@c000 {
557 compatible = "qcom,pm8916-gpio";
558 reg = <0xc000 0x400>;
559 gpio-controller;
560 gpio-count = <4>;
561 #gpio-cells = <2>;
562 gpio-bank-name="spmi";
563 };
564 };
565 };
maxims@google.comdaea6d42017-04-17 12:00:21 -0700[diff] [blame]566
567 wdt0: wdt@0 {
568 compatible = "sandbox,wdt";
569 };
Rob Clarka471b672018-01-10 11:33:30 +0100[diff] [blame]570
Mario Six95922152018-08-09 14:51:19 +0200[diff] [blame]571 axi: axi@0 {
572 compatible = "sandbox,axi";
573 #address-cells = <0x1>;
574 #size-cells = <0x1>;
575 store@0 {
576 compatible = "sandbox,sandbox_store";
577 reg = <0x0 0x400>;
578 };
579 };
580
Rob Clarka471b672018-01-10 11:33:30 +0100[diff] [blame]581 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -0700[diff] [blame]582 #address-cells = <1>;
583 #size-cells = <1>;
Rob Clarka471b672018-01-10 11:33:30 +0100[diff] [blame]584 chosen-test {
585 compatible = "denx,u-boot-fdt-test";
586 reg = <9 1>;
587 };
588 };
Mario Six35616ef2018-03-12 14:53:33 +0100[diff] [blame]589
590 translation-test@8000 {
591 compatible = "simple-bus";
592 reg = <0x8000 0x4000>;
593
594 #address-cells = <0x2>;
595 #size-cells = <0x1>;
596
597 ranges = <0 0x0 0x8000 0x1000
598 1 0x100 0x9000 0x1000
599 2 0x200 0xA000 0x1000
600 3 0x300 0xB000 0x1000
601 >;
602
603 dev@0,0 {
604 compatible = "denx,u-boot-fdt-dummy";
605 reg = <0 0x0 0x1000>;
606 };
607
608 dev@1,100 {
609 compatible = "denx,u-boot-fdt-dummy";
610 reg = <1 0x100 0x1000>;
611
612 };
613
614 dev@2,200 {
615 compatible = "denx,u-boot-fdt-dummy";
616 reg = <2 0x200 0x1000>;
617 };
618
619
620 noxlatebus@3,300 {
621 compatible = "simple-bus";
622 reg = <3 0x300 0x1000>;
623
624 #address-cells = <0x1>;
625 #size-cells = <0x0>;
626
627 dev@42 {
628 compatible = "denx,u-boot-fdt-dummy";
629 reg = <0x42>;
630 };
631 };
632 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]633};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]634
635#include "sandbox_pmic.dtsi"