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git01.mediatek.com / filogic / uboot / 468ef08c7d61f6e306f1153334420b40bfa9e3fa / . / board / micronas / vct / dcgu.c
blob: e72d57f0e0808d9d5b52cbbf1a696611ccb56f18 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Stefan Roese9182d2f2009-01-21 17:24:39 +0100[diff] [blame]2/*
3 * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
4 *
5 * Original Author Guenter Gebhardt
6 * Copyright (C) 2006 Micronas GmbH
Stefan Roese9182d2f2009-01-21 17:24:39 +0100[diff] [blame]7 */
8
9#include <common.h>
Masahiro Yamada56a931c2016-09-21 11:28:55 +0900[diff] [blame]10#include <linux/errno.h>
Stefan Roese9182d2f2009-01-21 17:24:39 +0100[diff] [blame]11
12#include "vct.h"
13
14int dcgu_set_clk_switch(enum dcgu_hw_module module, enum dcgu_switch setup)
15{
16 u32 enable;
17 union dcgu_clk_en1 en1;
18 union dcgu_clk_en2 en2;
19
20 switch (setup) {
21 case DCGU_SWITCH_ON:
22 enable = 1;
23 break;
24 case DCGU_SWITCH_OFF:
25 enable = 0;
26 break;
27 default:
28 printf("%s:%i:Invalid clock switch: %i\n", __FILE__, __LINE__,
29 setup);
30 return -EINVAL;
31 }
32
33 if (module == DCGU_HW_MODULE_CPU)
34 en2.reg = reg_read(DCGU_CLK_EN2(DCGU_BASE));
35 else
36 en1.reg = reg_read(DCGU_CLK_EN1(DCGU_BASE));
37
38 switch (module) {
39 case DCGU_HW_MODULE_MSMC:
40 en1.bits.en_clkmsmc = enable;
41 break;
42 case DCGU_HW_MODULE_SSI_S:
43 en1.bits.en_clkssi_s = enable;
44 break;
45 case DCGU_HW_MODULE_SSI_M:
46 en1.bits.en_clkssi_m = enable;
47 break;
48 case DCGU_HW_MODULE_SMC:
49 en1.bits.en_clksmc = enable;
50 break;
51 case DCGU_HW_MODULE_EBI:
52 en1.bits.en_clkebi = enable;
53 break;
54 case DCGU_HW_MODULE_USB_PLL:
55 en1.bits.en_usbpll = enable;
56 break;
57 case DCGU_HW_MODULE_USB_60:
58 en1.bits.en_clkusb60 = enable;
59 break;
60 case DCGU_HW_MODULE_USB_24:
61 en1.bits.en_clkusb24 = enable;
62 break;
63 case DCGU_HW_MODULE_UART_2:
64 en1.bits.en_clkuart2 = enable;
65 break;
66 case DCGU_HW_MODULE_UART_1:
67 en1.bits.en_clkuart1 = enable;
68 break;
69 case DCGU_HW_MODULE_PERI:
70 en1.bits.en_clkperi20 = enable;
71 break;
72 case DCGU_HW_MODULE_CPU:
73 en2.bits.en_clkcpu = enable;
74 break;
75 case DCGU_HW_MODULE_I2S:
76 en1.bits.en_clk_i2s_dly = enable;
77 break;
78 case DCGU_HW_MODULE_ABP_SCC:
79 en1.bits.en_clk_scc_abp = enable;
80 break;
81 case DCGU_HW_MODULE_SPDIF:
82 en1.bits.en_clk_dtv_spdo = enable;
83 break;
84 case DCGU_HW_MODULE_AD:
85 en1.bits.en_clkad = enable;
86 break;
87 case DCGU_HW_MODULE_MVD:
88 en1.bits.en_clkmvd = enable;
89 break;
90 case DCGU_HW_MODULE_TSD:
91 en1.bits.en_clktsd = enable;
92 break;
93 case DCGU_HW_MODULE_GA:
94 en1.bits.en_clkga = enable;
95 break;
96 case DCGU_HW_MODULE_DVP:
97 en1.bits.en_clkdvp = enable;
98 break;
99 case DCGU_HW_MODULE_MR2:
100 en1.bits.en_clkmr2 = enable;
101 break;
102 case DCGU_HW_MODULE_MR1:
103 en1.bits.en_clkmr1 = enable;
104 break;
105 default:
106 printf("%s:%i:Invalid hardware module: %i\n", __FILE__,
107 __LINE__, module);
108 return -EINVAL;
109 }
110
111 /*
112 * The reg_read() following the reg_write() below forces the write to
113 * be really done on the bus.
114 * Otherwise the clock may not be switched on when this API function
115 * returns, which may cause an bus error if a registers of the hardware
116 * module connected to the clock is accessed.
117 */
118 if (module == DCGU_HW_MODULE_CPU) {
119 reg_write(DCGU_CLK_EN2(DCGU_BASE), en2.reg);
120 en2.reg = reg_read(DCGU_CLK_EN2(DCGU_BASE));
121 } else {
122 reg_write(DCGU_CLK_EN1(DCGU_BASE), en1.reg);
123 en1.reg = reg_read(DCGU_CLK_EN1(DCGU_BASE));
124 }
125
126 return 0;
127}
128
129int dcgu_set_reset_switch(enum dcgu_hw_module module, enum dcgu_switch setup)
130{
131 union dcgu_reset_unit1 val;
132 u32 enable;
133
134 switch (setup) {
135 case DCGU_SWITCH_ON:
136 enable = 1;
137 break;
138 case DCGU_SWITCH_OFF:
139 enable = 0;
140 break;
141 default:
142 printf("%s:%i:Invalid reset switch: %i\n", __FILE__, __LINE__,
143 setup);
144 return -EINVAL;
145 }
146
147 val.reg = reg_read(DCGU_RESET_UNIT1(DCGU_BASE));
148 switch (module) {
149 case DCGU_HW_MODULE_MSMC:
150 val.bits.swreset_clkmsmc = enable;
151 break;
152 case DCGU_HW_MODULE_SSI_S:
153 val.bits.swreset_clkssi_s = enable;
154 break;
155 case DCGU_HW_MODULE_SSI_M:
156 val.bits.swreset_clkssi_m = enable;
157 break;
158 case DCGU_HW_MODULE_SMC:
159 val.bits.swreset_clksmc = enable;
160 break;
161 case DCGU_HW_MODULE_EBI:
162 val.bits.swreset_clkebi = enable;
163 break;
164 case DCGU_HW_MODULE_USB_60:
165 val.bits.swreset_clkusb60 = enable;
166 break;
167 case DCGU_HW_MODULE_USB_24:
168 val.bits.swreset_clkusb24 = enable;
169 break;
170 case DCGU_HW_MODULE_UART_2:
171 val.bits.swreset_clkuart2 = enable;
172 break;
173 case DCGU_HW_MODULE_UART_1:
174 val.bits.swreset_clkuart1 = enable;
175 break;
176 case DCGU_HW_MODULE_PWM:
177 val.bits.swreset_pwm = enable;
178 break;
179 case DCGU_HW_MODULE_GPT:
180 val.bits.swreset_gpt = enable;
181 break;
182 case DCGU_HW_MODULE_I2C2:
183 val.bits.swreset_i2c2 = enable;
184 break;
185 case DCGU_HW_MODULE_I2C1:
186 val.bits.swreset_i2c1 = enable;
187 break;
188 case DCGU_HW_MODULE_GPIO2:
189 val.bits.swreset_gpio2 = enable;
190 break;
191 case DCGU_HW_MODULE_GPIO1:
192 val.bits.swreset_gpio1 = enable;
193 break;
194 case DCGU_HW_MODULE_CPU:
195 val.bits.swreset_clkcpu = enable;
196 break;
197 case DCGU_HW_MODULE_I2S:
198 val.bits.swreset_clk_i2s_dly = enable;
199 break;
200 case DCGU_HW_MODULE_ABP_SCC:
201 val.bits.swreset_clk_scc_abp = enable;
202 break;
203 case DCGU_HW_MODULE_SPDIF:
204 val.bits.swreset_clk_dtv_spdo = enable;
205 break;
206 case DCGU_HW_MODULE_AD:
207 val.bits.swreset_clkad = enable;
208 break;
209 case DCGU_HW_MODULE_MVD:
210 val.bits.swreset_clkmvd = enable;
211 break;
212 case DCGU_HW_MODULE_TSD:
213 val.bits.swreset_clktsd = enable;
214 break;
215 case DCGU_HW_MODULE_TSIO:
216 val.bits.swreset_clktsio = enable;
217 break;
218 case DCGU_HW_MODULE_GA:
219 val.bits.swreset_clkga = enable;
220 break;
221 case DCGU_HW_MODULE_MPC:
222 val.bits.swreset_clkmpc = enable;
223 break;
224 case DCGU_HW_MODULE_CVE:
225 val.bits.swreset_clkcve = enable;
226 break;
227 case DCGU_HW_MODULE_DVP:
228 val.bits.swreset_clkdvp = enable;
229 break;
230 case DCGU_HW_MODULE_MR2:
231 val.bits.swreset_clkmr2 = enable;
232 break;
233 case DCGU_HW_MODULE_MR1:
234 val.bits.swreset_clkmr1 = enable;
235 break;
236 default:
237 printf("%s:%i:Invalid hardware module: %i\n", __FILE__,
238 __LINE__, module);
239 return -EINVAL;
240 }
241 reg_write(DCGU_RESET_UNIT1(DCGU_BASE), val.reg);
242
243 return 0;
244}