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git01.mediatek.com / filogic / uboot / 46603416317890720666c7f20da4d158c1cac68d / . / arch / arm / mach-uniphier / clk / clk-pro5.c
blob: 874964b2d5bc04dd82232121b5254bb2dd89ed8e [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Masahiro Yamadad5167d52015-09-22 00:27:40 +0900[diff] [blame]2/*
3 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamadad5167d52015-09-22 00:27:40 +0900[diff] [blame]4 */
5
6#include <linux/io.h>
Masahiro Yamadaefdf3402016-01-09 01:51:13 +0900[diff] [blame]7
8#include "../init.h"
9#include "../sc-regs.h"
Masahiro Yamadad5167d52015-09-22 00:27:40 +0900[diff] [blame]10
Masahiro Yamada98905692016-03-30 20:17:02 +0900[diff] [blame]11void uniphier_pro5_clk_init(void)
Masahiro Yamadad5167d52015-09-22 00:27:40 +0900[diff] [blame]12{
13 u32 tmp;
14
15 /* deassert reset */
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]16 tmp = readl(sc_base + SC_RSTCTRL);
Masahiro Yamada260eda22017-10-14 02:21:17 +0900[diff] [blame]17#ifdef CONFIG_USB_DWC3_UNIPHIER
Masahiro Yamadad5167d52015-09-22 00:27:40 +0900[diff] [blame]18 tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO;
19#endif
20#ifdef CONFIG_NAND_DENALI
21 tmp |= SC_RSTCTRL_NRST_NAND;
22#endif
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]23 writel(tmp, sc_base + SC_RSTCTRL);
24 readl(sc_base + SC_RSTCTRL); /* dummy read */
Masahiro Yamadad5167d52015-09-22 00:27:40 +0900[diff] [blame]25
Masahiro Yamada260eda22017-10-14 02:21:17 +0900[diff] [blame]26#ifdef CONFIG_USB_DWC3_UNIPHIER
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]27 tmp = readl(sc_base + SC_RSTCTRL2);
Masahiro Yamadad5167d52015-09-22 00:27:40 +0900[diff] [blame]28 tmp |= SC_RSTCTRL2_NRST_USB3B1;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]29 writel(tmp, sc_base + SC_RSTCTRL2);
30 readl(sc_base + SC_RSTCTRL2); /* dummy read */
Masahiro Yamadad5167d52015-09-22 00:27:40 +0900[diff] [blame]31#endif
32
Masahiro Yamada1c6a5e42016-03-30 20:17:42 +0900[diff] [blame]33 /* provide clocks */
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]34 tmp = readl(sc_base + SC_CLKCTRL);
Masahiro Yamada260eda22017-10-14 02:21:17 +0900[diff] [blame]35#ifdef CONFIG_USB_DWC3_UNIPHIER
Masahiro Yamadad5167d52015-09-22 00:27:40 +0900[diff] [blame]36 tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
37 SC_CLKCTRL_CEN_GIO;
38#endif
39#ifdef CONFIG_NAND_DENALI
40 tmp |= SC_CLKCTRL_CEN_NAND;
41#endif
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]42 writel(tmp, sc_base + SC_CLKCTRL);
43 readl(sc_base + SC_CLKCTRL); /* dummy read */
Masahiro Yamadad5167d52015-09-22 00:27:40 +0900[diff] [blame]44}