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Minkyu Kangae6f0c62009-07-20 11:40:01 +09001/*
Steve Sakoman1ad21582010-06-08 13:07:46 -07002 * Board specific setup info
3 *
4 * (C) Copyright 2010
5 * Texas Instruments, <www.ti.com>
6 *
7 * Author :
8 * Aneesh V <aneesh@ti.com>
Minkyu Kangae6f0c62009-07-20 11:40:01 +09009 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
Tom Rini8eb48ff2013-03-14 11:15:25 +000029#include <config.h>
Sricharan9310ff72011-11-15 09:49:55 -050030#include <asm/arch/omap.h>
Joel A Fernandesb55759e2012-09-18 04:30:51 +000031#include <asm/arch/spl.h>
Aneesh Vfd8798b2012-03-08 07:20:18 +000032#include <linux/linkage.h>
Sricharan308fe922011-11-15 09:50:03 -050033
Aneesh Vfd8798b2012-03-08 07:20:18 +000034ENTRY(save_boot_params)
Aneesh V13a74c12011-07-21 09:10:27 -040035 /*
36 * See if the rom code passed pointer is valid:
37 * It is not valid if it is not in non-secure SRAM
38 * This may happen if you are booting with the help of
39 * debugger
40 */
41 ldr r2, =NON_SECURE_SRAM_START
42 cmp r2, r0
43 bgt 1f
44 ldr r2, =NON_SECURE_SRAM_END
45 cmp r2, r0
46 blt 1f
47
Sricharan308fe922011-11-15 09:50:03 -050048 /*
49 * store the boot params passed from rom code or saved
50 * and passed by SPL
51 */
52 cmp r0, #0
53 beq 1f
54 ldr r1, =boot_params
55 str r0, [r1]
56#ifdef CONFIG_SPL_BUILD
Tom Rini0be93ff2012-08-13 12:53:23 -070057 /* Store the boot device in spl_boot_device */
Sricharan308fe922011-11-15 09:50:03 -050058 ldrb r2, [r0, #BOOT_DEVICE_OFFSET] @ r1 <- value of boot device
Aneesh V13a74c12011-07-21 09:10:27 -040059 and r2, #BOOT_DEVICE_MASK
Sricharan308fe922011-11-15 09:50:03 -050060 ldr r3, =boot_params
Tom Rini0be93ff2012-08-13 12:53:23 -070061 strb r2, [r3, #BOOT_DEVICE_OFFSET] @ spl_boot_device <- r1
Aneesh V13a74c12011-07-21 09:10:27 -040062
Sricharan308fe922011-11-15 09:50:03 -050063 /* boot mode is passed only for devices that can raw/fat mode */
Joel A Fernandesb55759e2012-09-18 04:30:51 +000064 cmp r2, #BOOT_DEVICE_XIP
Sricharan308fe922011-11-15 09:50:03 -050065 blt 2f
Joel A Fernandesb55759e2012-09-18 04:30:51 +000066 cmp r2, #BOOT_DEVICE_MMC2
Sricharan308fe922011-11-15 09:50:03 -050067 bgt 2f
Tom Rini69fa4442012-08-14 09:20:06 -070068 /* Store the boot mode (raw/FAT) in omap_bootmode */
Aneesh V13a74c12011-07-21 09:10:27 -040069 ldr r2, [r0, #DEV_DESC_PTR_OFFSET] @ get the device descriptor ptr
70 ldr r2, [r2, #DEV_DATA_PTR_OFFSET] @ get the pDeviceData ptr
71 ldr r2, [r2, #BOOT_MODE_OFFSET] @ get the boot mode
Sricharan9310ff72011-11-15 09:49:55 -050072 ldr r3, =omap_bootmode
Aneesh V13a74c12011-07-21 09:10:27 -040073 str r2, [r3]
Sricharan308fe922011-11-15 09:50:03 -050074#endif
752:
76 ldrb r2, [r0, #CH_FLAGS_OFFSET]
77 ldr r3, =boot_params
78 strb r2, [r3, #CH_FLAGS_OFFSET]
Aneesh V13a74c12011-07-21 09:10:27 -0400791:
80 bx lr
Aneesh Vfd8798b2012-03-08 07:20:18 +000081ENDPROC(save_boot_params)
Sricharan308fe922011-11-15 09:50:03 -050082
Aneesh Vfd8798b2012-03-08 07:20:18 +000083ENTRY(set_pl310_ctrl_reg)
Aneesh Ve3405bd2011-06-16 23:30:52 +000084 PUSH {r4-r11, lr} @ save registers - ROM code may pollute
85 @ our registers
86 LDR r12, =0x102 @ Set PL310 control register - value in R0
87 .word 0xe1600070 @ SMC #0 - hand assembled because -march=armv5
88 @ call ROM Code API to set control register
89 POP {r4-r11, pc}
Aneesh Vfd8798b2012-03-08 07:20:18 +000090ENDPROC(set_pl310_ctrl_reg)