Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 1 | /* |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 2 | * Copyright 2013-2015 Freescale Semiconductor, Inc. |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 3 | * |
| 4 | * Freescale Quad Serial Peripheral Interface (QSPI) driver |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 7 | */ |
| 8 | |
| 9 | #include <common.h> |
| 10 | #include <malloc.h> |
| 11 | #include <spi.h> |
| 12 | #include <asm/io.h> |
| 13 | #include <linux/sizes.h> |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 14 | #include <dm.h> |
| 15 | #include <errno.h> |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 16 | #include "fsl_qspi.h" |
| 17 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 18 | DECLARE_GLOBAL_DATA_PTR; |
| 19 | |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 20 | #define RX_BUFFER_SIZE 0x80 |
Peng Fan | 828e468 | 2014-12-31 11:01:38 +0800 | [diff] [blame] | 21 | #ifdef CONFIG_MX6SX |
| 22 | #define TX_BUFFER_SIZE 0x200 |
| 23 | #else |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 24 | #define TX_BUFFER_SIZE 0x40 |
Peng Fan | 828e468 | 2014-12-31 11:01:38 +0800 | [diff] [blame] | 25 | #endif |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 26 | |
Jagan Teki | da1fdfd | 2015-10-23 01:02:04 +0530 | [diff] [blame] | 27 | #define OFFSET_BITS_MASK GENMASK(24, 0) |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 28 | |
| 29 | #define FLASH_STATUS_WEL 0x02 |
| 30 | |
| 31 | /* SEQID */ |
| 32 | #define SEQID_WREN 1 |
| 33 | #define SEQID_FAST_READ 2 |
| 34 | #define SEQID_RDSR 3 |
| 35 | #define SEQID_SE 4 |
| 36 | #define SEQID_CHIP_ERASE 5 |
| 37 | #define SEQID_PP 6 |
| 38 | #define SEQID_RDID 7 |
Peng Fan | 3642a87 | 2014-12-31 11:01:39 +0800 | [diff] [blame] | 39 | #define SEQID_BE_4K 8 |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 40 | #ifdef CONFIG_SPI_FLASH_BAR |
| 41 | #define SEQID_BRRD 9 |
| 42 | #define SEQID_BRWR 10 |
| 43 | #define SEQID_RDEAR 11 |
| 44 | #define SEQID_WREAR 12 |
| 45 | #endif |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 46 | |
Peng Fan | ff16234 | 2014-12-31 11:01:36 +0800 | [diff] [blame] | 47 | /* QSPI CMD */ |
| 48 | #define QSPI_CMD_PP 0x02 /* Page program (up to 256 bytes) */ |
| 49 | #define QSPI_CMD_RDSR 0x05 /* Read status register */ |
| 50 | #define QSPI_CMD_WREN 0x06 /* Write enable */ |
| 51 | #define QSPI_CMD_FAST_READ 0x0b /* Read data bytes (high frequency) */ |
Peng Fan | 3642a87 | 2014-12-31 11:01:39 +0800 | [diff] [blame] | 52 | #define QSPI_CMD_BE_4K 0x20 /* 4K erase */ |
Peng Fan | ff16234 | 2014-12-31 11:01:36 +0800 | [diff] [blame] | 53 | #define QSPI_CMD_CHIP_ERASE 0xc7 /* Erase whole flash chip */ |
| 54 | #define QSPI_CMD_SE 0xd8 /* Sector erase (usually 64KiB) */ |
| 55 | #define QSPI_CMD_RDID 0x9f /* Read JEDEC ID */ |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 56 | |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 57 | /* Used for Micron, winbond and Macronix flashes */ |
| 58 | #define QSPI_CMD_WREAR 0xc5 /* EAR register write */ |
| 59 | #define QSPI_CMD_RDEAR 0xc8 /* EAR reigster read */ |
| 60 | |
| 61 | /* Used for Spansion flashes only. */ |
| 62 | #define QSPI_CMD_BRRD 0x16 /* Bank register read */ |
| 63 | #define QSPI_CMD_BRWR 0x17 /* Bank register write */ |
| 64 | |
Peng Fan | ff16234 | 2014-12-31 11:01:36 +0800 | [diff] [blame] | 65 | /* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */ |
| 66 | #define QSPI_CMD_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */ |
| 67 | #define QSPI_CMD_PP_4B 0x12 /* Page program (up to 256 bytes) */ |
| 68 | #define QSPI_CMD_SE_4B 0xdc /* Sector erase (usually 64KiB) */ |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 69 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 70 | /* fsl_qspi_platdata flags */ |
Jagan Teki | c97ca92 | 2015-10-23 01:37:18 +0530 | [diff] [blame] | 71 | #define QSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0) |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 72 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 73 | /* default SCK frequency, unit: HZ */ |
| 74 | #define FSL_QSPI_DEFAULT_SCK_FREQ 50000000 |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 75 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 76 | /* QSPI max chipselect signals number */ |
| 77 | #define FSL_QSPI_MAX_CHIPSELECT_NUM 4 |
| 78 | |
| 79 | #ifdef CONFIG_DM_SPI |
| 80 | /** |
| 81 | * struct fsl_qspi_platdata - platform data for Freescale QSPI |
| 82 | * |
| 83 | * @flags: Flags for QSPI QSPI_FLAG_... |
| 84 | * @speed_hz: Default SCK frequency |
| 85 | * @reg_base: Base address of QSPI registers |
| 86 | * @amba_base: Base address of QSPI memory mapping |
| 87 | * @amba_total_size: size of QSPI memory mapping |
| 88 | * @flash_num: Number of active slave devices |
| 89 | * @num_chipselect: Number of QSPI chipselect signals |
| 90 | */ |
| 91 | struct fsl_qspi_platdata { |
| 92 | u32 flags; |
| 93 | u32 speed_hz; |
| 94 | u32 reg_base; |
| 95 | u32 amba_base; |
| 96 | u32 amba_total_size; |
| 97 | u32 flash_num; |
| 98 | u32 num_chipselect; |
| 99 | }; |
Peng Fan | 828e468 | 2014-12-31 11:01:38 +0800 | [diff] [blame] | 100 | #endif |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 101 | |
| 102 | /** |
| 103 | * struct fsl_qspi_priv - private data for Freescale QSPI |
| 104 | * |
| 105 | * @flags: Flags for QSPI QSPI_FLAG_... |
| 106 | * @bus_clk: QSPI input clk frequency |
| 107 | * @speed_hz: Default SCK frequency |
| 108 | * @cur_seqid: current LUT table sequence id |
| 109 | * @sf_addr: flash access offset |
| 110 | * @amba_base: Base address of QSPI memory mapping of every CS |
| 111 | * @amba_total_size: size of QSPI memory mapping |
| 112 | * @cur_amba_base: Base address of QSPI memory mapping of current CS |
| 113 | * @flash_num: Number of active slave devices |
| 114 | * @num_chipselect: Number of QSPI chipselect signals |
| 115 | * @regs: Point to QSPI register structure for I/O access |
| 116 | */ |
| 117 | struct fsl_qspi_priv { |
| 118 | u32 flags; |
| 119 | u32 bus_clk; |
| 120 | u32 speed_hz; |
| 121 | u32 cur_seqid; |
| 122 | u32 sf_addr; |
| 123 | u32 amba_base[FSL_QSPI_MAX_CHIPSELECT_NUM]; |
| 124 | u32 amba_total_size; |
| 125 | u32 cur_amba_base; |
| 126 | u32 flash_num; |
| 127 | u32 num_chipselect; |
| 128 | struct fsl_qspi_regs *regs; |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 129 | }; |
| 130 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 131 | #ifndef CONFIG_DM_SPI |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 132 | struct fsl_qspi { |
| 133 | struct spi_slave slave; |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 134 | struct fsl_qspi_priv priv; |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 135 | }; |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 136 | #endif |
| 137 | |
| 138 | static u32 qspi_read32(u32 flags, u32 *addr) |
| 139 | { |
| 140 | return flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? |
| 141 | in_be32(addr) : in_le32(addr); |
| 142 | } |
| 143 | |
| 144 | static void qspi_write32(u32 flags, u32 *addr, u32 val) |
| 145 | { |
| 146 | flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? |
| 147 | out_be32(addr, val) : out_le32(addr, val); |
| 148 | } |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 149 | |
| 150 | /* QSPI support swapping the flash read/write data |
| 151 | * in hardware for LS102xA, but not for VF610 */ |
| 152 | static inline u32 qspi_endian_xchg(u32 data) |
| 153 | { |
| 154 | #ifdef CONFIG_VF610 |
| 155 | return swab32(data); |
| 156 | #else |
| 157 | return data; |
| 158 | #endif |
| 159 | } |
| 160 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 161 | static void qspi_set_lut(struct fsl_qspi_priv *priv) |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 162 | { |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 163 | struct fsl_qspi_regs *regs = priv->regs; |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 164 | u32 lut_base; |
| 165 | |
| 166 | /* Unlock the LUT */ |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 167 | qspi_write32(priv->flags, ®s->lutkey, LUT_KEY_VALUE); |
| 168 | qspi_write32(priv->flags, ®s->lckcr, QSPI_LCKCR_UNLOCK); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 169 | |
| 170 | /* Write Enable */ |
| 171 | lut_base = SEQID_WREN * 4; |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 172 | qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_WREN) | |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 173 | PAD0(LUT_PAD1) | INSTR0(LUT_CMD)); |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 174 | qspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); |
| 175 | qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); |
| 176 | qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 177 | |
| 178 | /* Fast Read */ |
| 179 | lut_base = SEQID_FAST_READ * 4; |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 180 | #ifdef CONFIG_SPI_FLASH_BAR |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 181 | qspi_write32(priv->flags, ®s->lut[lut_base], |
| 182 | OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) | |
| 183 | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 184 | PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); |
| 185 | #else |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 186 | if (FSL_QSPI_FLASH_SIZE <= SZ_16M) |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 187 | qspi_write32(priv->flags, ®s->lut[lut_base], |
| 188 | OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) | |
| 189 | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | |
| 190 | PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 191 | else |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 192 | qspi_write32(priv->flags, ®s->lut[lut_base], |
Peng Fan | ff16234 | 2014-12-31 11:01:36 +0800 | [diff] [blame] | 193 | OPRND0(QSPI_CMD_FAST_READ_4B) | |
| 194 | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | |
| 195 | OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) | |
| 196 | INSTR1(LUT_ADDR)); |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 197 | #endif |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 198 | qspi_write32(priv->flags, ®s->lut[lut_base + 1], |
| 199 | OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) | |
| 200 | OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) | |
| 201 | INSTR1(LUT_READ)); |
| 202 | qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); |
| 203 | qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 204 | |
| 205 | /* Read Status */ |
| 206 | lut_base = SEQID_RDSR * 4; |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 207 | qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_RDSR) | |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 208 | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | |
| 209 | PAD1(LUT_PAD1) | INSTR1(LUT_READ)); |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 210 | qspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); |
| 211 | qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); |
| 212 | qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 213 | |
| 214 | /* Erase a sector */ |
| 215 | lut_base = SEQID_SE * 4; |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 216 | #ifdef CONFIG_SPI_FLASH_BAR |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 217 | qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_SE) | |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 218 | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | |
| 219 | PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); |
| 220 | #else |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 221 | if (FSL_QSPI_FLASH_SIZE <= SZ_16M) |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 222 | qspi_write32(priv->flags, ®s->lut[lut_base], |
| 223 | OPRND0(QSPI_CMD_SE) | PAD0(LUT_PAD1) | |
| 224 | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | |
| 225 | PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 226 | else |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 227 | qspi_write32(priv->flags, ®s->lut[lut_base], |
| 228 | OPRND0(QSPI_CMD_SE_4B) | PAD0(LUT_PAD1) | |
| 229 | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | |
| 230 | PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 231 | #endif |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 232 | qspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); |
| 233 | qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); |
| 234 | qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 235 | |
| 236 | /* Erase the whole chip */ |
| 237 | lut_base = SEQID_CHIP_ERASE * 4; |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 238 | qspi_write32(priv->flags, ®s->lut[lut_base], |
| 239 | OPRND0(QSPI_CMD_CHIP_ERASE) | |
| 240 | PAD0(LUT_PAD1) | INSTR0(LUT_CMD)); |
| 241 | qspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); |
| 242 | qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); |
| 243 | qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 244 | |
| 245 | /* Page Program */ |
| 246 | lut_base = SEQID_PP * 4; |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 247 | #ifdef CONFIG_SPI_FLASH_BAR |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 248 | qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_PP) | |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 249 | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | |
| 250 | PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); |
| 251 | #else |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 252 | if (FSL_QSPI_FLASH_SIZE <= SZ_16M) |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 253 | qspi_write32(priv->flags, ®s->lut[lut_base], |
| 254 | OPRND0(QSPI_CMD_PP) | PAD0(LUT_PAD1) | |
| 255 | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | |
| 256 | PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 257 | else |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 258 | qspi_write32(priv->flags, ®s->lut[lut_base], |
| 259 | OPRND0(QSPI_CMD_PP_4B) | PAD0(LUT_PAD1) | |
| 260 | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | |
| 261 | PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 262 | #endif |
Peng Fan | 828e468 | 2014-12-31 11:01:38 +0800 | [diff] [blame] | 263 | #ifdef CONFIG_MX6SX |
| 264 | /* |
| 265 | * To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly. |
| 266 | * So, Use IDATSZ in IPCR to determine the size and here set 0. |
| 267 | */ |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 268 | qspi_write32(priv->flags, ®s->lut[lut_base + 1], OPRND0(0) | |
Peng Fan | 828e468 | 2014-12-31 11:01:38 +0800 | [diff] [blame] | 269 | PAD0(LUT_PAD1) | INSTR0(LUT_WRITE)); |
| 270 | #else |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 271 | qspi_write32(priv->flags, ®s->lut[lut_base + 1], |
| 272 | OPRND0(TX_BUFFER_SIZE) | |
| 273 | PAD0(LUT_PAD1) | INSTR0(LUT_WRITE)); |
Peng Fan | 828e468 | 2014-12-31 11:01:38 +0800 | [diff] [blame] | 274 | #endif |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 275 | qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); |
| 276 | qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 277 | |
| 278 | /* READ ID */ |
| 279 | lut_base = SEQID_RDID * 4; |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 280 | qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_RDID) | |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 281 | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(8) | |
| 282 | PAD1(LUT_PAD1) | INSTR1(LUT_READ)); |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 283 | qspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); |
| 284 | qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); |
| 285 | qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 286 | |
Peng Fan | 3642a87 | 2014-12-31 11:01:39 +0800 | [diff] [blame] | 287 | /* SUB SECTOR 4K ERASE */ |
| 288 | lut_base = SEQID_BE_4K * 4; |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 289 | qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_BE_4K) | |
Peng Fan | 3642a87 | 2014-12-31 11:01:39 +0800 | [diff] [blame] | 290 | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | |
| 291 | PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); |
| 292 | |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 293 | #ifdef CONFIG_SPI_FLASH_BAR |
| 294 | /* |
| 295 | * BRRD BRWR RDEAR WREAR are all supported, because it is hard to |
| 296 | * dynamically check whether to set BRRD BRWR or RDEAR WREAR during |
| 297 | * initialization. |
| 298 | */ |
| 299 | lut_base = SEQID_BRRD * 4; |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 300 | qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_BRRD) | |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 301 | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | |
| 302 | PAD1(LUT_PAD1) | INSTR1(LUT_READ)); |
| 303 | |
| 304 | lut_base = SEQID_BRWR * 4; |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 305 | qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_BRWR) | |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 306 | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | |
| 307 | PAD1(LUT_PAD1) | INSTR1(LUT_WRITE)); |
| 308 | |
| 309 | lut_base = SEQID_RDEAR * 4; |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 310 | qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_RDEAR) | |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 311 | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | |
| 312 | PAD1(LUT_PAD1) | INSTR1(LUT_READ)); |
| 313 | |
| 314 | lut_base = SEQID_WREAR * 4; |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 315 | qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_WREAR) | |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 316 | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | |
| 317 | PAD1(LUT_PAD1) | INSTR1(LUT_WRITE)); |
| 318 | #endif |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 319 | /* Lock the LUT */ |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 320 | qspi_write32(priv->flags, ®s->lutkey, LUT_KEY_VALUE); |
| 321 | qspi_write32(priv->flags, ®s->lckcr, QSPI_LCKCR_LOCK); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 322 | } |
| 323 | |
Peng Fan | 1c5f966 | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 324 | #if defined(CONFIG_SYS_FSL_QSPI_AHB) |
| 325 | /* |
| 326 | * If we have changed the content of the flash by writing or erasing, |
| 327 | * we need to invalidate the AHB buffer. If we do not do so, we may read out |
| 328 | * the wrong data. The spec tells us reset the AHB domain and Serial Flash |
| 329 | * domain at the same time. |
| 330 | */ |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 331 | static inline void qspi_ahb_invalid(struct fsl_qspi_priv *priv) |
Peng Fan | 1c5f966 | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 332 | { |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 333 | struct fsl_qspi_regs *regs = priv->regs; |
Peng Fan | 1c5f966 | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 334 | u32 reg; |
| 335 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 336 | reg = qspi_read32(priv->flags, ®s->mcr); |
Peng Fan | 1c5f966 | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 337 | reg |= QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK; |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 338 | qspi_write32(priv->flags, ®s->mcr, reg); |
Peng Fan | 1c5f966 | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 339 | |
| 340 | /* |
| 341 | * The minimum delay : 1 AHB + 2 SFCK clocks. |
| 342 | * Delay 1 us is enough. |
| 343 | */ |
| 344 | udelay(1); |
| 345 | |
| 346 | reg &= ~(QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK); |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 347 | qspi_write32(priv->flags, ®s->mcr, reg); |
Peng Fan | 1c5f966 | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 348 | } |
| 349 | |
| 350 | /* Read out the data from the AHB buffer. */ |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 351 | static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len) |
Peng Fan | 1c5f966 | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 352 | { |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 353 | struct fsl_qspi_regs *regs = priv->regs; |
Peng Fan | 1c5f966 | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 354 | u32 mcr_reg; |
| 355 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 356 | mcr_reg = qspi_read32(priv->flags, ®s->mcr); |
Peng Fan | 1c5f966 | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 357 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 358 | qspi_write32(priv->flags, ®s->mcr, |
| 359 | QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | |
Peng Fan | 1c5f966 | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 360 | QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); |
| 361 | |
| 362 | /* Read out the data directly from the AHB buffer. */ |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 363 | memcpy(rxbuf, (u8 *)(priv->cur_amba_base + priv->sf_addr), len); |
Peng Fan | 1c5f966 | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 364 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 365 | qspi_write32(priv->flags, ®s->mcr, mcr_reg); |
Peng Fan | 1c5f966 | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 366 | } |
| 367 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 368 | static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv) |
Peng Fan | 1c5f966 | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 369 | { |
| 370 | u32 reg, reg2; |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 371 | struct fsl_qspi_regs *regs = priv->regs; |
Peng Fan | 1c5f966 | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 372 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 373 | reg = qspi_read32(priv->flags, ®s->mcr); |
Peng Fan | 1c5f966 | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 374 | /* Disable the module */ |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 375 | qspi_write32(priv->flags, ®s->mcr, reg | QSPI_MCR_MDIS_MASK); |
Peng Fan | 1c5f966 | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 376 | |
| 377 | /* Set the Sampling Register for DDR */ |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 378 | reg2 = qspi_read32(priv->flags, ®s->smpr); |
Peng Fan | 1c5f966 | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 379 | reg2 &= ~QSPI_SMPR_DDRSMP_MASK; |
| 380 | reg2 |= (2 << QSPI_SMPR_DDRSMP_SHIFT); |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 381 | qspi_write32(priv->flags, ®s->smpr, reg2); |
Peng Fan | 1c5f966 | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 382 | |
| 383 | /* Enable the module again (enable the DDR too) */ |
| 384 | reg |= QSPI_MCR_DDR_EN_MASK; |
| 385 | /* Enable bit 29 for imx6sx */ |
Jagan Teki | c97ca92 | 2015-10-23 01:37:18 +0530 | [diff] [blame] | 386 | reg |= BIT(29); |
Peng Fan | 1c5f966 | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 387 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 388 | qspi_write32(priv->flags, ®s->mcr, reg); |
Peng Fan | 1c5f966 | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 389 | } |
| 390 | |
| 391 | /* |
| 392 | * There are two different ways to read out the data from the flash: |
| 393 | * the "IP Command Read" and the "AHB Command Read". |
| 394 | * |
| 395 | * The IC guy suggests we use the "AHB Command Read" which is faster |
| 396 | * then the "IP Command Read". (What's more is that there is a bug in |
| 397 | * the "IP Command Read" in the Vybrid.) |
| 398 | * |
| 399 | * After we set up the registers for the "AHB Command Read", we can use |
| 400 | * the memcpy to read the data directly. A "missed" access to the buffer |
| 401 | * causes the controller to clear the buffer, and use the sequence pointed |
| 402 | * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash. |
| 403 | */ |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 404 | static void qspi_init_ahb_read(struct fsl_qspi_priv *priv) |
Peng Fan | 1c5f966 | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 405 | { |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 406 | struct fsl_qspi_regs *regs = priv->regs; |
| 407 | |
Peng Fan | 1c5f966 | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 408 | /* AHB configuration for access buffer 0/1/2 .*/ |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 409 | qspi_write32(priv->flags, ®s->buf0cr, QSPI_BUFXCR_INVALID_MSTRID); |
| 410 | qspi_write32(priv->flags, ®s->buf1cr, QSPI_BUFXCR_INVALID_MSTRID); |
| 411 | qspi_write32(priv->flags, ®s->buf2cr, QSPI_BUFXCR_INVALID_MSTRID); |
| 412 | qspi_write32(priv->flags, ®s->buf3cr, QSPI_BUF3CR_ALLMST_MASK | |
Peng Fan | 1c5f966 | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 413 | (0x80 << QSPI_BUF3CR_ADATSZ_SHIFT)); |
| 414 | |
| 415 | /* We only use the buffer3 */ |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 416 | qspi_write32(priv->flags, ®s->buf0ind, 0); |
| 417 | qspi_write32(priv->flags, ®s->buf1ind, 0); |
| 418 | qspi_write32(priv->flags, ®s->buf2ind, 0); |
Peng Fan | 1c5f966 | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 419 | |
| 420 | /* |
| 421 | * Set the default lut sequence for AHB Read. |
| 422 | * Parallel mode is disabled. |
| 423 | */ |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 424 | qspi_write32(priv->flags, ®s->bfgencr, |
Peng Fan | 1c5f966 | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 425 | SEQID_FAST_READ << QSPI_BFGENCR_SEQID_SHIFT); |
| 426 | |
| 427 | /*Enable DDR Mode*/ |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 428 | qspi_enable_ddr_mode(priv); |
Peng Fan | 1c5f966 | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 429 | } |
| 430 | #endif |
| 431 | |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 432 | #ifdef CONFIG_SPI_FLASH_BAR |
| 433 | /* Bank register read/write, EAR register read/write */ |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 434 | static void qspi_op_rdbank(struct fsl_qspi_priv *priv, u8 *rxbuf, u32 len) |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 435 | { |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 436 | struct fsl_qspi_regs *regs = priv->regs; |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 437 | u32 reg, mcr_reg, data, seqid; |
| 438 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 439 | mcr_reg = qspi_read32(priv->flags, ®s->mcr); |
| 440 | qspi_write32(priv->flags, ®s->mcr, |
| 441 | QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 442 | QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 443 | qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 444 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 445 | qspi_write32(priv->flags, ®s->sfar, priv->cur_amba_base); |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 446 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 447 | if (priv->cur_seqid == QSPI_CMD_BRRD) |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 448 | seqid = SEQID_BRRD; |
| 449 | else |
| 450 | seqid = SEQID_RDEAR; |
| 451 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 452 | qspi_write32(priv->flags, ®s->ipcr, |
| 453 | (seqid << QSPI_IPCR_SEQID_SHIFT) | len); |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 454 | |
| 455 | /* Wait previous command complete */ |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 456 | while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 457 | ; |
| 458 | |
| 459 | while (1) { |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 460 | reg = qspi_read32(priv->flags, ®s->rbsr); |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 461 | if (reg & QSPI_RBSR_RDBFL_MASK) { |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 462 | data = qspi_read32(priv->flags, ®s->rbdr[0]); |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 463 | data = qspi_endian_xchg(data); |
| 464 | memcpy(rxbuf, &data, len); |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 465 | qspi_write32(priv->flags, ®s->mcr, |
| 466 | qspi_read32(priv->flags, ®s->mcr) | |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 467 | QSPI_MCR_CLR_RXF_MASK); |
| 468 | break; |
| 469 | } |
| 470 | } |
| 471 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 472 | qspi_write32(priv->flags, ®s->mcr, mcr_reg); |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 473 | } |
| 474 | #endif |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 475 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 476 | static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len) |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 477 | { |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 478 | struct fsl_qspi_regs *regs = priv->regs; |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 479 | u32 mcr_reg, rbsr_reg, data; |
| 480 | int i, size; |
| 481 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 482 | mcr_reg = qspi_read32(priv->flags, ®s->mcr); |
| 483 | qspi_write32(priv->flags, ®s->mcr, |
| 484 | QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | |
| 485 | QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); |
| 486 | qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 487 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 488 | qspi_write32(priv->flags, ®s->sfar, priv->cur_amba_base); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 489 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 490 | qspi_write32(priv->flags, ®s->ipcr, |
| 491 | (SEQID_RDID << QSPI_IPCR_SEQID_SHIFT) | 0); |
| 492 | while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 493 | ; |
| 494 | |
| 495 | i = 0; |
| 496 | size = len; |
| 497 | while ((RX_BUFFER_SIZE >= size) && (size > 0)) { |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 498 | rbsr_reg = qspi_read32(priv->flags, ®s->rbsr); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 499 | if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) { |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 500 | data = qspi_read32(priv->flags, ®s->rbdr[i]); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 501 | data = qspi_endian_xchg(data); |
| 502 | memcpy(rxbuf, &data, 4); |
| 503 | rxbuf++; |
| 504 | size -= 4; |
| 505 | i++; |
| 506 | } |
| 507 | } |
| 508 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 509 | qspi_write32(priv->flags, ®s->mcr, mcr_reg); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 510 | } |
| 511 | |
Peng Fan | 1c5f966 | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 512 | #ifndef CONFIG_SYS_FSL_QSPI_AHB |
| 513 | /* If not use AHB read, read data from ip interface */ |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 514 | static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len) |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 515 | { |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 516 | struct fsl_qspi_regs *regs = priv->regs; |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 517 | u32 mcr_reg, data; |
| 518 | int i, size; |
| 519 | u32 to_or_from; |
| 520 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 521 | mcr_reg = qspi_read32(priv->flags, ®s->mcr); |
| 522 | qspi_write32(priv->flags, ®s->mcr, |
| 523 | QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | |
| 524 | QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); |
| 525 | qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 526 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 527 | to_or_from = priv->sf_addr + priv->cur_amba_base; |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 528 | |
| 529 | while (len > 0) { |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 530 | qspi_write32(priv->flags, ®s->sfar, to_or_from); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 531 | |
| 532 | size = (len > RX_BUFFER_SIZE) ? |
| 533 | RX_BUFFER_SIZE : len; |
| 534 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 535 | qspi_write32(priv->flags, ®s->ipcr, |
| 536 | (SEQID_FAST_READ << QSPI_IPCR_SEQID_SHIFT) | |
| 537 | size); |
| 538 | while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 539 | ; |
| 540 | |
| 541 | to_or_from += size; |
| 542 | len -= size; |
| 543 | |
| 544 | i = 0; |
| 545 | while ((RX_BUFFER_SIZE >= size) && (size > 0)) { |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 546 | data = qspi_read32(priv->flags, ®s->rbdr[i]); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 547 | data = qspi_endian_xchg(data); |
| 548 | memcpy(rxbuf, &data, 4); |
| 549 | rxbuf++; |
| 550 | size -= 4; |
| 551 | i++; |
| 552 | } |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 553 | qspi_write32(priv->flags, ®s->mcr, |
| 554 | qspi_read32(priv->flags, ®s->mcr) | |
| 555 | QSPI_MCR_CLR_RXF_MASK); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 556 | } |
| 557 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 558 | qspi_write32(priv->flags, ®s->mcr, mcr_reg); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 559 | } |
Peng Fan | 1c5f966 | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 560 | #endif |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 561 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 562 | static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len) |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 563 | { |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 564 | struct fsl_qspi_regs *regs = priv->regs; |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 565 | u32 mcr_reg, data, reg, status_reg, seqid; |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 566 | int i, size, tx_size; |
| 567 | u32 to_or_from = 0; |
| 568 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 569 | mcr_reg = qspi_read32(priv->flags, ®s->mcr); |
| 570 | qspi_write32(priv->flags, ®s->mcr, |
| 571 | QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | |
| 572 | QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); |
| 573 | qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 574 | |
| 575 | status_reg = 0; |
| 576 | while ((status_reg & FLASH_STATUS_WEL) != FLASH_STATUS_WEL) { |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 577 | qspi_write32(priv->flags, ®s->ipcr, |
| 578 | (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0); |
| 579 | while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 580 | ; |
| 581 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 582 | qspi_write32(priv->flags, ®s->ipcr, |
| 583 | (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 1); |
| 584 | while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 585 | ; |
| 586 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 587 | reg = qspi_read32(priv->flags, ®s->rbsr); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 588 | if (reg & QSPI_RBSR_RDBFL_MASK) { |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 589 | status_reg = qspi_read32(priv->flags, ®s->rbdr[0]); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 590 | status_reg = qspi_endian_xchg(status_reg); |
| 591 | } |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 592 | qspi_write32(priv->flags, ®s->mcr, |
| 593 | qspi_read32(priv->flags, ®s->mcr) | |
| 594 | QSPI_MCR_CLR_RXF_MASK); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 595 | } |
| 596 | |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 597 | /* Default is page programming */ |
| 598 | seqid = SEQID_PP; |
| 599 | #ifdef CONFIG_SPI_FLASH_BAR |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 600 | if (priv->cur_seqid == QSPI_CMD_BRWR) |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 601 | seqid = SEQID_BRWR; |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 602 | else if (priv->cur_seqid == QSPI_CMD_WREAR) |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 603 | seqid = SEQID_WREAR; |
| 604 | #endif |
| 605 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 606 | to_or_from = priv->sf_addr + priv->cur_amba_base; |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 607 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 608 | qspi_write32(priv->flags, ®s->sfar, to_or_from); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 609 | |
| 610 | tx_size = (len > TX_BUFFER_SIZE) ? |
| 611 | TX_BUFFER_SIZE : len; |
| 612 | |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 613 | size = tx_size / 4; |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 614 | for (i = 0; i < size; i++) { |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 615 | memcpy(&data, txbuf, 4); |
| 616 | data = qspi_endian_xchg(data); |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 617 | qspi_write32(priv->flags, ®s->tbdr, data); |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 618 | txbuf += 4; |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 619 | } |
| 620 | |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 621 | size = tx_size % 4; |
| 622 | if (size) { |
| 623 | data = 0; |
| 624 | memcpy(&data, txbuf, size); |
| 625 | data = qspi_endian_xchg(data); |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 626 | qspi_write32(priv->flags, ®s->tbdr, data); |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 627 | } |
| 628 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 629 | qspi_write32(priv->flags, ®s->ipcr, |
| 630 | (seqid << QSPI_IPCR_SEQID_SHIFT) | tx_size); |
| 631 | while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 632 | ; |
| 633 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 634 | qspi_write32(priv->flags, ®s->mcr, mcr_reg); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 635 | } |
| 636 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 637 | static void qspi_op_rdsr(struct fsl_qspi_priv *priv, u32 *rxbuf) |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 638 | { |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 639 | struct fsl_qspi_regs *regs = priv->regs; |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 640 | u32 mcr_reg, reg, data; |
| 641 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 642 | mcr_reg = qspi_read32(priv->flags, ®s->mcr); |
| 643 | qspi_write32(priv->flags, ®s->mcr, |
| 644 | QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | |
| 645 | QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); |
| 646 | qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 647 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 648 | qspi_write32(priv->flags, ®s->sfar, priv->cur_amba_base); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 649 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 650 | qspi_write32(priv->flags, ®s->ipcr, |
| 651 | (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 0); |
| 652 | while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 653 | ; |
| 654 | |
| 655 | while (1) { |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 656 | reg = qspi_read32(priv->flags, ®s->rbsr); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 657 | if (reg & QSPI_RBSR_RDBFL_MASK) { |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 658 | data = qspi_read32(priv->flags, ®s->rbdr[0]); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 659 | data = qspi_endian_xchg(data); |
| 660 | memcpy(rxbuf, &data, 4); |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 661 | qspi_write32(priv->flags, ®s->mcr, |
| 662 | qspi_read32(priv->flags, ®s->mcr) | |
| 663 | QSPI_MCR_CLR_RXF_MASK); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 664 | break; |
| 665 | } |
| 666 | } |
| 667 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 668 | qspi_write32(priv->flags, ®s->mcr, mcr_reg); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 669 | } |
| 670 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 671 | static void qspi_op_erase(struct fsl_qspi_priv *priv) |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 672 | { |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 673 | struct fsl_qspi_regs *regs = priv->regs; |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 674 | u32 mcr_reg; |
| 675 | u32 to_or_from = 0; |
| 676 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 677 | mcr_reg = qspi_read32(priv->flags, ®s->mcr); |
| 678 | qspi_write32(priv->flags, ®s->mcr, |
| 679 | QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | |
| 680 | QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); |
| 681 | qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 682 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 683 | to_or_from = priv->sf_addr + priv->cur_amba_base; |
| 684 | qspi_write32(priv->flags, ®s->sfar, to_or_from); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 685 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 686 | qspi_write32(priv->flags, ®s->ipcr, |
| 687 | (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0); |
| 688 | while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 689 | ; |
| 690 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 691 | if (priv->cur_seqid == QSPI_CMD_SE) { |
| 692 | qspi_write32(priv->flags, ®s->ipcr, |
Peng Fan | 3642a87 | 2014-12-31 11:01:39 +0800 | [diff] [blame] | 693 | (SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0); |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 694 | } else if (priv->cur_seqid == QSPI_CMD_BE_4K) { |
| 695 | qspi_write32(priv->flags, ®s->ipcr, |
Peng Fan | 3642a87 | 2014-12-31 11:01:39 +0800 | [diff] [blame] | 696 | (SEQID_BE_4K << QSPI_IPCR_SEQID_SHIFT) | 0); |
| 697 | } |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 698 | while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 699 | ; |
| 700 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 701 | qspi_write32(priv->flags, ®s->mcr, mcr_reg); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 702 | } |
| 703 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 704 | int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen, |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 705 | const void *dout, void *din, unsigned long flags) |
| 706 | { |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 707 | u32 bytes = DIV_ROUND_UP(bitlen, 8); |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 708 | static u32 wr_sfaddr; |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 709 | u32 txbuf; |
| 710 | |
| 711 | if (dout) { |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 712 | if (flags & SPI_XFER_BEGIN) { |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 713 | priv->cur_seqid = *(u8 *)dout; |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 714 | memcpy(&txbuf, dout, 4); |
| 715 | } |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 716 | |
| 717 | if (flags == SPI_XFER_END) { |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 718 | priv->sf_addr = wr_sfaddr; |
| 719 | qspi_op_write(priv, (u8 *)dout, bytes); |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 720 | return 0; |
| 721 | } |
| 722 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 723 | if (priv->cur_seqid == QSPI_CMD_FAST_READ) { |
| 724 | priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK; |
| 725 | } else if ((priv->cur_seqid == QSPI_CMD_SE) || |
| 726 | (priv->cur_seqid == QSPI_CMD_BE_4K)) { |
| 727 | priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK; |
| 728 | qspi_op_erase(priv); |
| 729 | } else if (priv->cur_seqid == QSPI_CMD_PP) { |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 730 | wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK; |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 731 | } else if ((priv->cur_seqid == QSPI_CMD_BRWR) || |
| 732 | (priv->cur_seqid == QSPI_CMD_WREAR)) { |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 733 | #ifdef CONFIG_SPI_FLASH_BAR |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 734 | wr_sfaddr = 0; |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 735 | #endif |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 736 | } |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 737 | } |
| 738 | |
| 739 | if (din) { |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 740 | if (priv->cur_seqid == QSPI_CMD_FAST_READ) { |
Peng Fan | 1c5f966 | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 741 | #ifdef CONFIG_SYS_FSL_QSPI_AHB |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 742 | qspi_ahb_read(priv, din, bytes); |
Peng Fan | 1c5f966 | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 743 | #else |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 744 | qspi_op_read(priv, din, bytes); |
Peng Fan | 1c5f966 | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 745 | #endif |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 746 | } else if (priv->cur_seqid == QSPI_CMD_RDID) |
| 747 | qspi_op_rdid(priv, din, bytes); |
| 748 | else if (priv->cur_seqid == QSPI_CMD_RDSR) |
| 749 | qspi_op_rdsr(priv, din); |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 750 | #ifdef CONFIG_SPI_FLASH_BAR |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 751 | else if ((priv->cur_seqid == QSPI_CMD_BRRD) || |
| 752 | (priv->cur_seqid == QSPI_CMD_RDEAR)) { |
| 753 | priv->sf_addr = 0; |
| 754 | qspi_op_rdbank(priv, din, bytes); |
Peng Fan | 3a34448 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 755 | } |
| 756 | #endif |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 757 | } |
| 758 | |
Peng Fan | 1c5f966 | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 759 | #ifdef CONFIG_SYS_FSL_QSPI_AHB |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 760 | if ((priv->cur_seqid == QSPI_CMD_SE) || |
| 761 | (priv->cur_seqid == QSPI_CMD_PP) || |
| 762 | (priv->cur_seqid == QSPI_CMD_BE_4K) || |
| 763 | (priv->cur_seqid == QSPI_CMD_WREAR) || |
| 764 | (priv->cur_seqid == QSPI_CMD_BRWR)) |
| 765 | qspi_ahb_invalid(priv); |
| 766 | #endif |
| 767 | |
| 768 | return 0; |
| 769 | } |
| 770 | |
| 771 | void qspi_module_disable(struct fsl_qspi_priv *priv, u8 disable) |
| 772 | { |
| 773 | u32 mcr_val; |
| 774 | |
| 775 | mcr_val = qspi_read32(priv->flags, &priv->regs->mcr); |
| 776 | if (disable) |
| 777 | mcr_val |= QSPI_MCR_MDIS_MASK; |
| 778 | else |
| 779 | mcr_val &= ~QSPI_MCR_MDIS_MASK; |
| 780 | qspi_write32(priv->flags, &priv->regs->mcr, mcr_val); |
| 781 | } |
| 782 | |
| 783 | void qspi_cfg_smpr(struct fsl_qspi_priv *priv, u32 clear_bits, u32 set_bits) |
| 784 | { |
| 785 | u32 smpr_val; |
| 786 | |
| 787 | smpr_val = qspi_read32(priv->flags, &priv->regs->smpr); |
| 788 | smpr_val &= ~clear_bits; |
| 789 | smpr_val |= set_bits; |
| 790 | qspi_write32(priv->flags, &priv->regs->smpr, smpr_val); |
| 791 | } |
| 792 | #ifndef CONFIG_DM_SPI |
| 793 | static unsigned long spi_bases[] = { |
| 794 | QSPI0_BASE_ADDR, |
| 795 | #ifdef CONFIG_MX6SX |
| 796 | QSPI1_BASE_ADDR, |
| 797 | #endif |
| 798 | }; |
| 799 | |
| 800 | static unsigned long amba_bases[] = { |
| 801 | QSPI0_AMBA_BASE, |
| 802 | #ifdef CONFIG_MX6SX |
| 803 | QSPI1_AMBA_BASE, |
| 804 | #endif |
| 805 | }; |
| 806 | |
| 807 | static inline struct fsl_qspi *to_qspi_spi(struct spi_slave *slave) |
| 808 | { |
| 809 | return container_of(slave, struct fsl_qspi, slave); |
| 810 | } |
| 811 | |
| 812 | struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, |
| 813 | unsigned int max_hz, unsigned int mode) |
| 814 | { |
| 815 | struct fsl_qspi *qspi; |
| 816 | struct fsl_qspi_regs *regs; |
| 817 | u32 total_size; |
| 818 | |
| 819 | if (bus >= ARRAY_SIZE(spi_bases)) |
| 820 | return NULL; |
| 821 | |
| 822 | if (cs >= FSL_QSPI_FLASH_NUM) |
| 823 | return NULL; |
| 824 | |
| 825 | qspi = spi_alloc_slave(struct fsl_qspi, bus, cs); |
| 826 | if (!qspi) |
| 827 | return NULL; |
| 828 | |
| 829 | #ifdef CONFIG_SYS_FSL_QSPI_BE |
| 830 | qspi->priv.flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG; |
| 831 | #endif |
| 832 | |
| 833 | regs = (struct fsl_qspi_regs *)spi_bases[bus]; |
| 834 | qspi->priv.regs = regs; |
| 835 | /* |
| 836 | * According cs, use different amba_base to choose the |
| 837 | * corresponding flash devices. |
| 838 | * |
| 839 | * If not, only one flash device is used even if passing |
| 840 | * different cs using `sf probe` |
| 841 | */ |
| 842 | qspi->priv.cur_amba_base = amba_bases[bus] + cs * FSL_QSPI_FLASH_SIZE; |
| 843 | |
| 844 | qspi->slave.max_write_size = TX_BUFFER_SIZE; |
| 845 | |
| 846 | qspi_write32(qspi->priv.flags, ®s->mcr, |
| 847 | QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK); |
| 848 | |
| 849 | qspi_cfg_smpr(&qspi->priv, |
| 850 | ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK | |
| 851 | QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0); |
| 852 | |
| 853 | total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM; |
| 854 | /* |
| 855 | * Any read access to non-implemented addresses will provide |
| 856 | * undefined results. |
| 857 | * |
| 858 | * In case single die flash devices, TOP_ADDR_MEMA2 and |
| 859 | * TOP_ADDR_MEMB2 should be initialized/programmed to |
| 860 | * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect, |
| 861 | * setting the size of these devices to 0. This would ensure |
| 862 | * that the complete memory map is assigned to only one flash device. |
| 863 | */ |
| 864 | qspi_write32(qspi->priv.flags, ®s->sfa1ad, |
| 865 | FSL_QSPI_FLASH_SIZE | amba_bases[bus]); |
| 866 | qspi_write32(qspi->priv.flags, ®s->sfa2ad, |
| 867 | FSL_QSPI_FLASH_SIZE | amba_bases[bus]); |
| 868 | qspi_write32(qspi->priv.flags, ®s->sfb1ad, |
| 869 | total_size | amba_bases[bus]); |
| 870 | qspi_write32(qspi->priv.flags, ®s->sfb2ad, |
| 871 | total_size | amba_bases[bus]); |
| 872 | |
| 873 | qspi_set_lut(&qspi->priv); |
| 874 | |
| 875 | #ifdef CONFIG_SYS_FSL_QSPI_AHB |
| 876 | qspi_init_ahb_read(&qspi->priv); |
Peng Fan | 1c5f966 | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 877 | #endif |
| 878 | |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 879 | qspi_module_disable(&qspi->priv, 0); |
| 880 | |
| 881 | return &qspi->slave; |
| 882 | } |
| 883 | |
| 884 | void spi_free_slave(struct spi_slave *slave) |
| 885 | { |
| 886 | struct fsl_qspi *qspi = to_qspi_spi(slave); |
| 887 | |
| 888 | free(qspi); |
| 889 | } |
| 890 | |
| 891 | int spi_claim_bus(struct spi_slave *slave) |
| 892 | { |
Alison Wang | c7410e3 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 893 | return 0; |
| 894 | } |
| 895 | |
| 896 | void spi_release_bus(struct spi_slave *slave) |
| 897 | { |
| 898 | /* Nothing to do */ |
| 899 | } |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 900 | |
| 901 | int spi_xfer(struct spi_slave *slave, unsigned int bitlen, |
| 902 | const void *dout, void *din, unsigned long flags) |
| 903 | { |
| 904 | struct fsl_qspi *qspi = to_qspi_spi(slave); |
| 905 | |
| 906 | return qspi_xfer(&qspi->priv, bitlen, dout, din, flags); |
| 907 | } |
| 908 | |
| 909 | void spi_init(void) |
| 910 | { |
| 911 | /* Nothing to do */ |
| 912 | } |
| 913 | #else |
| 914 | static int fsl_qspi_child_pre_probe(struct udevice *dev) |
| 915 | { |
Simon Glass | de44acf | 2015-09-28 23:32:01 -0600 | [diff] [blame] | 916 | struct spi_slave *slave = dev_get_parent_priv(dev); |
Haikun.Wang@freescale.com | 221f2e1 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 917 | |
| 918 | slave->max_write_size = TX_BUFFER_SIZE; |
| 919 | |
| 920 | return 0; |
| 921 | } |
| 922 | |
| 923 | static int fsl_qspi_probe(struct udevice *bus) |
| 924 | { |
| 925 | u32 total_size; |
| 926 | struct fsl_qspi_platdata *plat = dev_get_platdata(bus); |
| 927 | struct fsl_qspi_priv *priv = dev_get_priv(bus); |
| 928 | struct dm_spi_bus *dm_spi_bus; |
| 929 | |
| 930 | dm_spi_bus = bus->uclass_priv; |
| 931 | |
| 932 | dm_spi_bus->max_hz = plat->speed_hz; |
| 933 | |
| 934 | priv->regs = (struct fsl_qspi_regs *)plat->reg_base; |
| 935 | priv->flags = plat->flags; |
| 936 | |
| 937 | priv->speed_hz = plat->speed_hz; |
| 938 | priv->amba_base[0] = plat->amba_base; |
| 939 | priv->amba_total_size = plat->amba_total_size; |
| 940 | priv->flash_num = plat->flash_num; |
| 941 | priv->num_chipselect = plat->num_chipselect; |
| 942 | |
| 943 | qspi_write32(priv->flags, &priv->regs->mcr, |
| 944 | QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK); |
| 945 | |
| 946 | qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK | |
| 947 | QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0); |
| 948 | |
| 949 | total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM; |
| 950 | /* |
| 951 | * Any read access to non-implemented addresses will provide |
| 952 | * undefined results. |
| 953 | * |
| 954 | * In case single die flash devices, TOP_ADDR_MEMA2 and |
| 955 | * TOP_ADDR_MEMB2 should be initialized/programmed to |
| 956 | * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect, |
| 957 | * setting the size of these devices to 0. This would ensure |
| 958 | * that the complete memory map is assigned to only one flash device. |
| 959 | */ |
| 960 | qspi_write32(priv->flags, &priv->regs->sfa1ad, |
| 961 | FSL_QSPI_FLASH_SIZE | priv->amba_base[0]); |
| 962 | qspi_write32(priv->flags, &priv->regs->sfa2ad, |
| 963 | FSL_QSPI_FLASH_SIZE | priv->amba_base[0]); |
| 964 | qspi_write32(priv->flags, &priv->regs->sfb1ad, |
| 965 | total_size | priv->amba_base[0]); |
| 966 | qspi_write32(priv->flags, &priv->regs->sfb2ad, |
| 967 | total_size | priv->amba_base[0]); |
| 968 | |
| 969 | qspi_set_lut(priv); |
| 970 | |
| 971 | #ifdef CONFIG_SYS_FSL_QSPI_AHB |
| 972 | qspi_init_ahb_read(priv); |
| 973 | #endif |
| 974 | |
| 975 | qspi_module_disable(priv, 0); |
| 976 | |
| 977 | return 0; |
| 978 | } |
| 979 | |
| 980 | static int fsl_qspi_ofdata_to_platdata(struct udevice *bus) |
| 981 | { |
| 982 | struct reg_data { |
| 983 | u32 addr; |
| 984 | u32 size; |
| 985 | } regs_data[2]; |
| 986 | struct fsl_qspi_platdata *plat = bus->platdata; |
| 987 | const void *blob = gd->fdt_blob; |
| 988 | int node = bus->of_offset; |
| 989 | int ret, flash_num = 0, subnode; |
| 990 | |
| 991 | if (fdtdec_get_bool(blob, node, "big-endian")) |
| 992 | plat->flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG; |
| 993 | |
| 994 | ret = fdtdec_get_int_array(blob, node, "reg", (u32 *)regs_data, |
| 995 | sizeof(regs_data)/sizeof(u32)); |
| 996 | if (ret) { |
| 997 | debug("Error: can't get base addresses (ret = %d)!\n", ret); |
| 998 | return -ENOMEM; |
| 999 | } |
| 1000 | |
| 1001 | /* Count flash numbers */ |
| 1002 | fdt_for_each_subnode(blob, subnode, node) |
| 1003 | ++flash_num; |
| 1004 | |
| 1005 | if (flash_num == 0) { |
| 1006 | debug("Error: Missing flashes!\n"); |
| 1007 | return -ENODEV; |
| 1008 | } |
| 1009 | |
| 1010 | plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency", |
| 1011 | FSL_QSPI_DEFAULT_SCK_FREQ); |
| 1012 | plat->num_chipselect = fdtdec_get_int(blob, node, "num-cs", |
| 1013 | FSL_QSPI_MAX_CHIPSELECT_NUM); |
| 1014 | |
| 1015 | plat->reg_base = regs_data[0].addr; |
| 1016 | plat->amba_base = regs_data[1].addr; |
| 1017 | plat->amba_total_size = regs_data[1].size; |
| 1018 | plat->flash_num = flash_num; |
| 1019 | |
| 1020 | debug("%s: regs=<0x%x> <0x%x, 0x%x>, max-frequency=%d, endianess=%s\n", |
| 1021 | __func__, |
| 1022 | plat->reg_base, |
| 1023 | plat->amba_base, |
| 1024 | plat->amba_total_size, |
| 1025 | plat->speed_hz, |
| 1026 | plat->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le" |
| 1027 | ); |
| 1028 | |
| 1029 | return 0; |
| 1030 | } |
| 1031 | |
| 1032 | static int fsl_qspi_xfer(struct udevice *dev, unsigned int bitlen, |
| 1033 | const void *dout, void *din, unsigned long flags) |
| 1034 | { |
| 1035 | struct fsl_qspi_priv *priv; |
| 1036 | struct udevice *bus; |
| 1037 | |
| 1038 | bus = dev->parent; |
| 1039 | priv = dev_get_priv(bus); |
| 1040 | |
| 1041 | return qspi_xfer(priv, bitlen, dout, din, flags); |
| 1042 | } |
| 1043 | |
| 1044 | static int fsl_qspi_claim_bus(struct udevice *dev) |
| 1045 | { |
| 1046 | struct fsl_qspi_priv *priv; |
| 1047 | struct udevice *bus; |
| 1048 | struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); |
| 1049 | |
| 1050 | bus = dev->parent; |
| 1051 | priv = dev_get_priv(bus); |
| 1052 | |
| 1053 | priv->cur_amba_base = |
| 1054 | priv->amba_base[0] + FSL_QSPI_FLASH_SIZE * slave_plat->cs; |
| 1055 | |
| 1056 | qspi_module_disable(priv, 0); |
| 1057 | |
| 1058 | return 0; |
| 1059 | } |
| 1060 | |
| 1061 | static int fsl_qspi_release_bus(struct udevice *dev) |
| 1062 | { |
| 1063 | struct fsl_qspi_priv *priv; |
| 1064 | struct udevice *bus; |
| 1065 | |
| 1066 | bus = dev->parent; |
| 1067 | priv = dev_get_priv(bus); |
| 1068 | |
| 1069 | qspi_module_disable(priv, 1); |
| 1070 | |
| 1071 | return 0; |
| 1072 | } |
| 1073 | |
| 1074 | static int fsl_qspi_set_speed(struct udevice *bus, uint speed) |
| 1075 | { |
| 1076 | /* Nothing to do */ |
| 1077 | return 0; |
| 1078 | } |
| 1079 | |
| 1080 | static int fsl_qspi_set_mode(struct udevice *bus, uint mode) |
| 1081 | { |
| 1082 | /* Nothing to do */ |
| 1083 | return 0; |
| 1084 | } |
| 1085 | |
| 1086 | static const struct dm_spi_ops fsl_qspi_ops = { |
| 1087 | .claim_bus = fsl_qspi_claim_bus, |
| 1088 | .release_bus = fsl_qspi_release_bus, |
| 1089 | .xfer = fsl_qspi_xfer, |
| 1090 | .set_speed = fsl_qspi_set_speed, |
| 1091 | .set_mode = fsl_qspi_set_mode, |
| 1092 | }; |
| 1093 | |
| 1094 | static const struct udevice_id fsl_qspi_ids[] = { |
| 1095 | { .compatible = "fsl,vf610-qspi" }, |
| 1096 | { .compatible = "fsl,imx6sx-qspi" }, |
| 1097 | { } |
| 1098 | }; |
| 1099 | |
| 1100 | U_BOOT_DRIVER(fsl_qspi) = { |
| 1101 | .name = "fsl_qspi", |
| 1102 | .id = UCLASS_SPI, |
| 1103 | .of_match = fsl_qspi_ids, |
| 1104 | .ops = &fsl_qspi_ops, |
| 1105 | .ofdata_to_platdata = fsl_qspi_ofdata_to_platdata, |
| 1106 | .platdata_auto_alloc_size = sizeof(struct fsl_qspi_platdata), |
| 1107 | .priv_auto_alloc_size = sizeof(struct fsl_qspi_priv), |
| 1108 | .probe = fsl_qspi_probe, |
| 1109 | .child_pre_probe = fsl_qspi_child_pre_probe, |
| 1110 | }; |
| 1111 | #endif |