Fabio Estevam | 77e6289 | 2012-09-13 03:18:20 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * Author: Fabio Estevam <fabio.estevam@freescale.com> |
| 5 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 6 | * SPDX-License-Identifier: GPL-2.0+ |
Fabio Estevam | 77e6289 | 2012-09-13 03:18:20 +0000 | [diff] [blame] | 7 | */ |
| 8 | |
Fabio Estevam | 77e6289 | 2012-09-13 03:18:20 +0000 | [diff] [blame] | 9 | #include <asm/arch/clock.h> |
| 10 | #include <asm/arch/imx-regs.h> |
| 11 | #include <asm/arch/iomux.h> |
Pierre Aubert | ec10aed | 2013-06-04 09:00:15 +0200 | [diff] [blame] | 12 | #include <asm/arch/mx6-pins.h> |
Fabio Estevam | 77e6289 | 2012-09-13 03:18:20 +0000 | [diff] [blame] | 13 | #include <asm/errno.h> |
| 14 | #include <asm/gpio.h> |
Fabio Estevam | ba92ad6 | 2014-05-09 13:15:42 -0300 | [diff] [blame] | 15 | #include <asm/imx-common/mxc_i2c.h> |
Fabio Estevam | 77e6289 | 2012-09-13 03:18:20 +0000 | [diff] [blame] | 16 | #include <asm/imx-common/iomux-v3.h> |
Otavio Salvador | 5286337 | 2013-03-16 08:05:07 +0000 | [diff] [blame] | 17 | #include <asm/imx-common/boot_mode.h> |
Eric Benard | d6cabb2 | 2014-04-04 19:05:54 +0200 | [diff] [blame] | 18 | #include <asm/imx-common/video.h> |
Fabio Estevam | 77e6289 | 2012-09-13 03:18:20 +0000 | [diff] [blame] | 19 | #include <mmc.h> |
| 20 | #include <fsl_esdhc.h> |
| 21 | #include <miiphy.h> |
| 22 | #include <netdev.h> |
Pardeep Kumar Singla | 0b87ba0 | 2013-07-25 12:12:14 -0500 | [diff] [blame] | 23 | #include <asm/arch/mxc_hdmi.h> |
| 24 | #include <asm/arch/crm_regs.h> |
Pardeep Kumar Singla | 0b87ba0 | 2013-07-25 12:12:14 -0500 | [diff] [blame] | 25 | #include <asm/io.h> |
| 26 | #include <asm/arch/sys_proto.h> |
Fabio Estevam | ba92ad6 | 2014-05-09 13:15:42 -0300 | [diff] [blame] | 27 | #include <i2c.h> |
| 28 | #include <power/pmic.h> |
| 29 | #include <power/pfuze100_pmic.h> |
Ye.Li | 75e02f9 | 2014-11-06 16:29:00 +0800 | [diff] [blame] | 30 | #include "../common/pfuze.h" |
John Tobias | 0749155 | 2014-11-12 14:27:45 -0800 | [diff] [blame] | 31 | #include <asm/arch/mx6-ddr.h> |
Peng Fan | c9498fa | 2014-12-02 09:55:27 +0800 | [diff] [blame] | 32 | #include <usb.h> |
John Tobias | 0749155 | 2014-11-12 14:27:45 -0800 | [diff] [blame] | 33 | |
Fabio Estevam | 77e6289 | 2012-09-13 03:18:20 +0000 | [diff] [blame] | 34 | DECLARE_GLOBAL_DATA_PTR; |
| 35 | |
Benoît Thébaudeau | 2167024 | 2013-04-26 01:34:47 +0000 | [diff] [blame] | 36 | #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
| 37 | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ |
| 38 | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
Fabio Estevam | 77e6289 | 2012-09-13 03:18:20 +0000 | [diff] [blame] | 39 | |
Benoît Thébaudeau | 2167024 | 2013-04-26 01:34:47 +0000 | [diff] [blame] | 40 | #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ |
| 41 | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ |
| 42 | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
Fabio Estevam | 77e6289 | 2012-09-13 03:18:20 +0000 | [diff] [blame] | 43 | |
Benoît Thébaudeau | 2167024 | 2013-04-26 01:34:47 +0000 | [diff] [blame] | 44 | #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
| 45 | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) |
Fabio Estevam | 77e6289 | 2012-09-13 03:18:20 +0000 | [diff] [blame] | 46 | |
Fabio Estevam | d82dad4 | 2013-11-08 16:20:54 -0200 | [diff] [blame] | 47 | #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ |
| 48 | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) |
| 49 | |
Fabio Estevam | ba92ad6 | 2014-05-09 13:15:42 -0300 | [diff] [blame] | 50 | #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
| 51 | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ |
| 52 | PAD_CTL_ODE | PAD_CTL_SRE_FAST) |
| 53 | |
| 54 | #define I2C_PMIC 1 |
| 55 | |
| 56 | #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) |
| 57 | |
Fabio Estevam | 0d29cee | 2014-10-21 21:14:53 -0200 | [diff] [blame] | 58 | #define DISP0_PWR_EN IMX_GPIO_NR(1, 21) |
| 59 | |
Fabio Estevam | 77e6289 | 2012-09-13 03:18:20 +0000 | [diff] [blame] | 60 | int dram_init(void) |
| 61 | { |
John Tobias | 0749155 | 2014-11-12 14:27:45 -0800 | [diff] [blame] | 62 | gd->ram_size = imx_ddr_size(); |
Fabio Estevam | 77e6289 | 2012-09-13 03:18:20 +0000 | [diff] [blame] | 63 | return 0; |
| 64 | } |
| 65 | |
Fabio Estevam | f533c2e | 2014-11-06 12:24:25 -0200 | [diff] [blame] | 66 | static iomux_v3_cfg_t const uart1_pads[] = { |
Eric Nelson | 3d3be0a | 2013-11-04 17:00:51 -0700 | [diff] [blame] | 67 | MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 68 | MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), |
Fabio Estevam | 77e6289 | 2012-09-13 03:18:20 +0000 | [diff] [blame] | 69 | }; |
| 70 | |
Fabio Estevam | f533c2e | 2014-11-06 12:24:25 -0200 | [diff] [blame] | 71 | static iomux_v3_cfg_t const enet_pads[] = { |
Eric Nelson | afea2ba | 2013-02-19 10:07:01 +0000 | [diff] [blame] | 72 | MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 73 | MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
Eric Nelson | 3d3be0a | 2013-11-04 17:00:51 -0700 | [diff] [blame] | 74 | MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 75 | MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 76 | MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 77 | MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 78 | MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
Eric Nelson | afea2ba | 2013-02-19 10:07:01 +0000 | [diff] [blame] | 79 | MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 80 | MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), |
Eric Nelson | 3d3be0a | 2013-11-04 17:00:51 -0700 | [diff] [blame] | 81 | MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 82 | MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 83 | MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 84 | MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 85 | MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
Eric Nelson | afea2ba | 2013-02-19 10:07:01 +0000 | [diff] [blame] | 86 | MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), |
Fabio Estevam | 2ebe246 | 2012-09-18 17:24:23 +0000 | [diff] [blame] | 87 | /* AR8031 PHY Reset */ |
Eric Nelson | 3d3be0a | 2013-11-04 17:00:51 -0700 | [diff] [blame] | 88 | MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), |
Fabio Estevam | 2ebe246 | 2012-09-18 17:24:23 +0000 | [diff] [blame] | 89 | }; |
| 90 | |
| 91 | static void setup_iomux_enet(void) |
| 92 | { |
| 93 | imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); |
| 94 | |
| 95 | /* Reset AR8031 PHY */ |
| 96 | gpio_direction_output(IMX_GPIO_NR(1, 25) , 0); |
Fabio Estevam | 66d4272 | 2016-01-05 17:02:53 -0200 | [diff] [blame] | 97 | mdelay(10); |
Fabio Estevam | 2ebe246 | 2012-09-18 17:24:23 +0000 | [diff] [blame] | 98 | gpio_set_value(IMX_GPIO_NR(1, 25), 1); |
Fabio Estevam | 66d4272 | 2016-01-05 17:02:53 -0200 | [diff] [blame] | 99 | udelay(100); |
Fabio Estevam | 2ebe246 | 2012-09-18 17:24:23 +0000 | [diff] [blame] | 100 | } |
| 101 | |
Fabio Estevam | f533c2e | 2014-11-06 12:24:25 -0200 | [diff] [blame] | 102 | static iomux_v3_cfg_t const usdhc2_pads[] = { |
Eric Nelson | 3d3be0a | 2013-11-04 17:00:51 -0700 | [diff] [blame] | 103 | MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 104 | MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 105 | MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 106 | MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 107 | MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 108 | MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 109 | MX6_PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 110 | MX6_PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 111 | MX6_PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 112 | MX6_PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 113 | MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ |
Shawn Guo | 7e5e833 | 2012-12-30 14:14:59 +0000 | [diff] [blame] | 114 | }; |
| 115 | |
Fabio Estevam | f533c2e | 2014-11-06 12:24:25 -0200 | [diff] [blame] | 116 | static iomux_v3_cfg_t const usdhc3_pads[] = { |
Eric Nelson | 3d3be0a | 2013-11-04 17:00:51 -0700 | [diff] [blame] | 117 | MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 118 | MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 119 | MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 120 | MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 121 | MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 122 | MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 123 | MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 124 | MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 125 | MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 126 | MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 127 | MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ |
Fabio Estevam | 77e6289 | 2012-09-13 03:18:20 +0000 | [diff] [blame] | 128 | }; |
| 129 | |
Fabio Estevam | f533c2e | 2014-11-06 12:24:25 -0200 | [diff] [blame] | 130 | static iomux_v3_cfg_t const usdhc4_pads[] = { |
Eric Nelson | 3d3be0a | 2013-11-04 17:00:51 -0700 | [diff] [blame] | 131 | MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 132 | MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 133 | MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 134 | MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 135 | MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 136 | MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 137 | MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 138 | MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 139 | MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 140 | MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
Shawn Guo | 7e5e833 | 2012-12-30 14:14:59 +0000 | [diff] [blame] | 141 | }; |
| 142 | |
Fabio Estevam | f533c2e | 2014-11-06 12:24:25 -0200 | [diff] [blame] | 143 | static iomux_v3_cfg_t const ecspi1_pads[] = { |
Fabio Estevam | d82dad4 | 2013-11-08 16:20:54 -0200 | [diff] [blame] | 144 | MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| 145 | MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| 146 | MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| 147 | MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 148 | }; |
| 149 | |
Fabio Estevam | 0d29cee | 2014-10-21 21:14:53 -0200 | [diff] [blame] | 150 | static iomux_v3_cfg_t const rgb_pads[] = { |
| 151 | MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 152 | MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 153 | MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 154 | MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 155 | MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 156 | MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 157 | MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 158 | MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 159 | MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 160 | MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 161 | MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 162 | MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 163 | MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 164 | MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 165 | MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 166 | MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 167 | MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 168 | MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 169 | MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 170 | MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 171 | MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 172 | MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 173 | MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 174 | MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 175 | MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 176 | MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 177 | MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 178 | MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 179 | MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 180 | MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 181 | }; |
| 182 | |
| 183 | static void enable_rgb(struct display_info_t const *dev) |
| 184 | { |
| 185 | imx_iomux_v3_setup_multiple_pads(rgb_pads, ARRAY_SIZE(rgb_pads)); |
| 186 | gpio_direction_output(DISP0_PWR_EN, 1); |
| 187 | } |
| 188 | |
Fabio Estevam | ba92ad6 | 2014-05-09 13:15:42 -0300 | [diff] [blame] | 189 | static struct i2c_pads_info i2c_pad_info1 = { |
| 190 | .scl = { |
| 191 | .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, |
| 192 | .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD, |
| 193 | .gp = IMX_GPIO_NR(4, 12) |
| 194 | }, |
| 195 | .sda = { |
| 196 | .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, |
| 197 | .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, |
| 198 | .gp = IMX_GPIO_NR(4, 13) |
| 199 | } |
| 200 | }; |
| 201 | |
Fabio Estevam | d82dad4 | 2013-11-08 16:20:54 -0200 | [diff] [blame] | 202 | static void setup_spi(void) |
| 203 | { |
| 204 | imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); |
| 205 | } |
| 206 | |
Marek Vasut | 0e99f01 | 2014-03-23 22:45:41 +0100 | [diff] [blame] | 207 | iomux_v3_cfg_t const pcie_pads[] = { |
| 208 | MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), /* POWER */ |
| 209 | MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */ |
| 210 | }; |
| 211 | |
| 212 | static void setup_pcie(void) |
| 213 | { |
| 214 | imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); |
| 215 | } |
| 216 | |
Fabio Estevam | dee3c84 | 2013-12-04 01:08:16 -0200 | [diff] [blame] | 217 | iomux_v3_cfg_t const di0_pads[] = { |
| 218 | MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */ |
| 219 | MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */ |
| 220 | MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* DISP0_VSYNC */ |
| 221 | }; |
| 222 | |
Fabio Estevam | 77e6289 | 2012-09-13 03:18:20 +0000 | [diff] [blame] | 223 | static void setup_iomux_uart(void) |
| 224 | { |
| 225 | imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); |
| 226 | } |
| 227 | |
| 228 | #ifdef CONFIG_FSL_ESDHC |
Shawn Guo | 7e5e833 | 2012-12-30 14:14:59 +0000 | [diff] [blame] | 229 | struct fsl_esdhc_cfg usdhc_cfg[3] = { |
| 230 | {USDHC2_BASE_ADDR}, |
Fabio Estevam | 77e6289 | 2012-09-13 03:18:20 +0000 | [diff] [blame] | 231 | {USDHC3_BASE_ADDR}, |
Shawn Guo | 7e5e833 | 2012-12-30 14:14:59 +0000 | [diff] [blame] | 232 | {USDHC4_BASE_ADDR}, |
Fabio Estevam | 77e6289 | 2012-09-13 03:18:20 +0000 | [diff] [blame] | 233 | }; |
| 234 | |
Shawn Guo | 7e5e833 | 2012-12-30 14:14:59 +0000 | [diff] [blame] | 235 | #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2) |
| 236 | #define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0) |
| 237 | |
Peng Fan | 03a43df | 2016-01-28 16:51:27 +0800 | [diff] [blame] | 238 | int board_mmc_get_env_dev(int devno) |
| 239 | { |
| 240 | return devno - 1; |
| 241 | } |
| 242 | |
Fabio Estevam | 77e6289 | 2012-09-13 03:18:20 +0000 | [diff] [blame] | 243 | int board_mmc_getcd(struct mmc *mmc) |
| 244 | { |
Shawn Guo | 7e5e833 | 2012-12-30 14:14:59 +0000 | [diff] [blame] | 245 | struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
Otavio Salvador | c2bed64 | 2013-03-16 08:05:06 +0000 | [diff] [blame] | 246 | int ret = 0; |
Shawn Guo | 7e5e833 | 2012-12-30 14:14:59 +0000 | [diff] [blame] | 247 | |
| 248 | switch (cfg->esdhc_base) { |
| 249 | case USDHC2_BASE_ADDR: |
Otavio Salvador | c2bed64 | 2013-03-16 08:05:06 +0000 | [diff] [blame] | 250 | ret = !gpio_get_value(USDHC2_CD_GPIO); |
| 251 | break; |
Shawn Guo | 7e5e833 | 2012-12-30 14:14:59 +0000 | [diff] [blame] | 252 | case USDHC3_BASE_ADDR: |
Otavio Salvador | c2bed64 | 2013-03-16 08:05:06 +0000 | [diff] [blame] | 253 | ret = !gpio_get_value(USDHC3_CD_GPIO); |
| 254 | break; |
| 255 | case USDHC4_BASE_ADDR: |
| 256 | ret = 1; /* eMMC/uSDHC4 is always present */ |
| 257 | break; |
Shawn Guo | 7e5e833 | 2012-12-30 14:14:59 +0000 | [diff] [blame] | 258 | } |
Otavio Salvador | c2bed64 | 2013-03-16 08:05:06 +0000 | [diff] [blame] | 259 | |
| 260 | return ret; |
Fabio Estevam | 77e6289 | 2012-09-13 03:18:20 +0000 | [diff] [blame] | 261 | } |
| 262 | |
| 263 | int board_mmc_init(bd_t *bis) |
| 264 | { |
John Tobias | 0749155 | 2014-11-12 14:27:45 -0800 | [diff] [blame] | 265 | #ifndef CONFIG_SPL_BUILD |
Fabio Estevam | 593d0c8 | 2014-11-06 12:24:24 -0200 | [diff] [blame] | 266 | int ret; |
Shawn Guo | 7e5e833 | 2012-12-30 14:14:59 +0000 | [diff] [blame] | 267 | int i; |
| 268 | |
Otavio Salvador | a272dbf | 2013-03-16 08:05:05 +0000 | [diff] [blame] | 269 | /* |
| 270 | * According to the board_mmc_init() the following map is done: |
Bin Meng | 7557405 | 2016-02-05 19:30:11 -0800 | [diff] [blame] | 271 | * (U-Boot device node) (Physical Port) |
Otavio Salvador | a272dbf | 2013-03-16 08:05:05 +0000 | [diff] [blame] | 272 | * mmc0 SD2 |
| 273 | * mmc1 SD3 |
| 274 | * mmc2 eMMC |
| 275 | */ |
Shawn Guo | 7e5e833 | 2012-12-30 14:14:59 +0000 | [diff] [blame] | 276 | for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { |
| 277 | switch (i) { |
| 278 | case 0: |
| 279 | imx_iomux_v3_setup_multiple_pads( |
| 280 | usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); |
| 281 | gpio_direction_input(USDHC2_CD_GPIO); |
| 282 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); |
| 283 | break; |
| 284 | case 1: |
| 285 | imx_iomux_v3_setup_multiple_pads( |
| 286 | usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); |
| 287 | gpio_direction_input(USDHC3_CD_GPIO); |
| 288 | usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); |
| 289 | break; |
| 290 | case 2: |
| 291 | imx_iomux_v3_setup_multiple_pads( |
| 292 | usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); |
| 293 | usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); |
| 294 | break; |
| 295 | default: |
| 296 | printf("Warning: you configured more USDHC controllers" |
Otavio Salvador | a937e22 | 2013-04-19 03:41:58 +0000 | [diff] [blame] | 297 | "(%d) then supported by the board (%d)\n", |
| 298 | i + 1, CONFIG_SYS_FSL_USDHC_NUM); |
Fabio Estevam | 593d0c8 | 2014-11-06 12:24:24 -0200 | [diff] [blame] | 299 | return -EINVAL; |
Otavio Salvador | a937e22 | 2013-04-19 03:41:58 +0000 | [diff] [blame] | 300 | } |
Shawn Guo | 7e5e833 | 2012-12-30 14:14:59 +0000 | [diff] [blame] | 301 | |
Fabio Estevam | 593d0c8 | 2014-11-06 12:24:24 -0200 | [diff] [blame] | 302 | ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); |
| 303 | if (ret) |
| 304 | return ret; |
Shawn Guo | 7e5e833 | 2012-12-30 14:14:59 +0000 | [diff] [blame] | 305 | } |
Fabio Estevam | 77e6289 | 2012-09-13 03:18:20 +0000 | [diff] [blame] | 306 | |
Fabio Estevam | 593d0c8 | 2014-11-06 12:24:24 -0200 | [diff] [blame] | 307 | return 0; |
John Tobias | 0749155 | 2014-11-12 14:27:45 -0800 | [diff] [blame] | 308 | #else |
Fabio Estevam | 56cf36a | 2014-11-18 11:26:06 -0200 | [diff] [blame] | 309 | struct src *psrc = (struct src *)SRC_BASE_ADDR; |
| 310 | unsigned reg = readl(&psrc->sbmr1) >> 11; |
John Tobias | 0749155 | 2014-11-12 14:27:45 -0800 | [diff] [blame] | 311 | /* |
| 312 | * Upon reading BOOT_CFG register the following map is done: |
| 313 | * Bit 11 and 12 of BOOT_CFG register can determine the current |
| 314 | * mmc port |
| 315 | * 0x1 SD1 |
| 316 | * 0x2 SD2 |
| 317 | * 0x3 SD4 |
| 318 | */ |
| 319 | |
| 320 | switch (reg & 0x3) { |
| 321 | case 0x1: |
| 322 | imx_iomux_v3_setup_multiple_pads( |
| 323 | usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); |
| 324 | usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; |
| 325 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); |
| 326 | gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; |
| 327 | break; |
| 328 | case 0x2: |
| 329 | imx_iomux_v3_setup_multiple_pads( |
| 330 | usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); |
| 331 | usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; |
| 332 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); |
| 333 | gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; |
| 334 | break; |
| 335 | case 0x3: |
| 336 | imx_iomux_v3_setup_multiple_pads( |
| 337 | usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); |
| 338 | usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; |
| 339 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); |
| 340 | gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; |
| 341 | break; |
| 342 | } |
| 343 | |
| 344 | return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); |
| 345 | #endif |
Fabio Estevam | 77e6289 | 2012-09-13 03:18:20 +0000 | [diff] [blame] | 346 | } |
| 347 | #endif |
| 348 | |
Pardeep Kumar Singla | 0b87ba0 | 2013-07-25 12:12:14 -0500 | [diff] [blame] | 349 | #if defined(CONFIG_VIDEO_IPUV3) |
Fabio Estevam | 70f84b5 | 2013-11-25 10:34:26 -0200 | [diff] [blame] | 350 | static void disable_lvds(struct display_info_t const *dev) |
| 351 | { |
| 352 | struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; |
| 353 | |
| 354 | int reg = readl(&iomux->gpr[2]); |
| 355 | |
| 356 | reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK | |
| 357 | IOMUXC_GPR2_LVDS_CH1_MODE_MASK); |
| 358 | |
| 359 | writel(reg, &iomux->gpr[2]); |
| 360 | } |
| 361 | |
Fabio Estevam | 9e642cd | 2013-09-04 15:12:38 -0300 | [diff] [blame] | 362 | static void do_enable_hdmi(struct display_info_t const *dev) |
| 363 | { |
Fabio Estevam | 70f84b5 | 2013-11-25 10:34:26 -0200 | [diff] [blame] | 364 | disable_lvds(dev); |
Fabio Estevam | 9e642cd | 2013-09-04 15:12:38 -0300 | [diff] [blame] | 365 | imx_enable_hdmi_phy(); |
| 366 | } |
Pardeep Kumar Singla | 0b87ba0 | 2013-07-25 12:12:14 -0500 | [diff] [blame] | 367 | |
Fabio Estevam | 9e642cd | 2013-09-04 15:12:38 -0300 | [diff] [blame] | 368 | static void enable_lvds(struct display_info_t const *dev) |
| 369 | { |
| 370 | struct iomuxc *iomux = (struct iomuxc *) |
| 371 | IOMUXC_BASE_ADDR; |
| 372 | u32 reg = readl(&iomux->gpr[2]); |
Fabio Estevam | 7d66d56 | 2013-12-04 01:08:17 -0200 | [diff] [blame] | 373 | reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | |
| 374 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT; |
Fabio Estevam | 9e642cd | 2013-09-04 15:12:38 -0300 | [diff] [blame] | 375 | writel(reg, &iomux->gpr[2]); |
| 376 | } |
Fabio Estevam | 70f84b5 | 2013-11-25 10:34:26 -0200 | [diff] [blame] | 377 | |
Eric Benard | d6cabb2 | 2014-04-04 19:05:54 +0200 | [diff] [blame] | 378 | struct display_info_t const displays[] = {{ |
Fabio Estevam | 9e642cd | 2013-09-04 15:12:38 -0300 | [diff] [blame] | 379 | .bus = -1, |
| 380 | .addr = 0, |
Fabio Estevam | 7d66d56 | 2013-12-04 01:08:17 -0200 | [diff] [blame] | 381 | .pixfmt = IPU_PIX_FMT_RGB666, |
Fabio Estevam | 70f84b5 | 2013-11-25 10:34:26 -0200 | [diff] [blame] | 382 | .detect = NULL, |
| 383 | .enable = enable_lvds, |
Fabio Estevam | 9e642cd | 2013-09-04 15:12:38 -0300 | [diff] [blame] | 384 | .mode = { |
Fabio Estevam | 70f84b5 | 2013-11-25 10:34:26 -0200 | [diff] [blame] | 385 | .name = "Hannstar-XGA", |
Fabio Estevam | 9e642cd | 2013-09-04 15:12:38 -0300 | [diff] [blame] | 386 | .refresh = 60, |
| 387 | .xres = 1024, |
| 388 | .yres = 768, |
| 389 | .pixclock = 15385, |
| 390 | .left_margin = 220, |
| 391 | .right_margin = 40, |
| 392 | .upper_margin = 21, |
| 393 | .lower_margin = 7, |
| 394 | .hsync_len = 60, |
| 395 | .vsync_len = 10, |
| 396 | .sync = FB_SYNC_EXT, |
| 397 | .vmode = FB_VMODE_NONINTERLACED |
| 398 | } }, { |
| 399 | .bus = -1, |
| 400 | .addr = 0, |
Fabio Estevam | 70f84b5 | 2013-11-25 10:34:26 -0200 | [diff] [blame] | 401 | .pixfmt = IPU_PIX_FMT_RGB24, |
| 402 | .detect = detect_hdmi, |
| 403 | .enable = do_enable_hdmi, |
Fabio Estevam | 9e642cd | 2013-09-04 15:12:38 -0300 | [diff] [blame] | 404 | .mode = { |
Fabio Estevam | 70f84b5 | 2013-11-25 10:34:26 -0200 | [diff] [blame] | 405 | .name = "HDMI", |
Fabio Estevam | 9e642cd | 2013-09-04 15:12:38 -0300 | [diff] [blame] | 406 | .refresh = 60, |
| 407 | .xres = 1024, |
| 408 | .yres = 768, |
| 409 | .pixclock = 15385, |
| 410 | .left_margin = 220, |
| 411 | .right_margin = 40, |
| 412 | .upper_margin = 21, |
| 413 | .lower_margin = 7, |
| 414 | .hsync_len = 60, |
| 415 | .vsync_len = 10, |
| 416 | .sync = FB_SYNC_EXT, |
| 417 | .vmode = FB_VMODE_NONINTERLACED |
Fabio Estevam | 0d29cee | 2014-10-21 21:14:53 -0200 | [diff] [blame] | 418 | } }, { |
| 419 | .bus = 0, |
| 420 | .addr = 0, |
| 421 | .pixfmt = IPU_PIX_FMT_RGB24, |
| 422 | .detect = NULL, |
| 423 | .enable = enable_rgb, |
| 424 | .mode = { |
| 425 | .name = "SEIKO-WVGA", |
| 426 | .refresh = 60, |
| 427 | .xres = 800, |
| 428 | .yres = 480, |
| 429 | .pixclock = 29850, |
| 430 | .left_margin = 89, |
| 431 | .right_margin = 164, |
| 432 | .upper_margin = 23, |
| 433 | .lower_margin = 10, |
| 434 | .hsync_len = 10, |
| 435 | .vsync_len = 10, |
| 436 | .sync = 0, |
| 437 | .vmode = FB_VMODE_NONINTERLACED |
Fabio Estevam | 9e642cd | 2013-09-04 15:12:38 -0300 | [diff] [blame] | 438 | } } }; |
Eric Benard | d6cabb2 | 2014-04-04 19:05:54 +0200 | [diff] [blame] | 439 | size_t display_count = ARRAY_SIZE(displays); |
Pardeep Kumar Singla | 0b87ba0 | 2013-07-25 12:12:14 -0500 | [diff] [blame] | 440 | |
| 441 | static void setup_display(void) |
| 442 | { |
| 443 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
Fabio Estevam | 9e642cd | 2013-09-04 15:12:38 -0300 | [diff] [blame] | 444 | struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; |
Pardeep Kumar Singla | 0b87ba0 | 2013-07-25 12:12:14 -0500 | [diff] [blame] | 445 | int reg; |
| 446 | |
Fabio Estevam | dee3c84 | 2013-12-04 01:08:16 -0200 | [diff] [blame] | 447 | /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */ |
| 448 | imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads)); |
| 449 | |
Pardeep Kumar Singla | 0b87ba0 | 2013-07-25 12:12:14 -0500 | [diff] [blame] | 450 | enable_ipu_clock(); |
| 451 | imx_setup_hdmi(); |
| 452 | |
Fabio Estevam | 9e642cd | 2013-09-04 15:12:38 -0300 | [diff] [blame] | 453 | /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */ |
Liu Ying | 6f45063 | 2013-11-29 22:38:39 +0800 | [diff] [blame] | 454 | reg = readl(&mxc_ccm->CCGR3); |
Fabio Estevam | 9e642cd | 2013-09-04 15:12:38 -0300 | [diff] [blame] | 455 | reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK; |
| 456 | writel(reg, &mxc_ccm->CCGR3); |
| 457 | |
| 458 | /* set LDB0, LDB1 clk select to 011/011 */ |
| 459 | reg = readl(&mxc_ccm->cs2cdr); |
| 460 | reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
| 461 | | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); |
| 462 | reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
| 463 | | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); |
| 464 | writel(reg, &mxc_ccm->cs2cdr); |
| 465 | |
| 466 | reg = readl(&mxc_ccm->cscmr2); |
| 467 | reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV; |
| 468 | writel(reg, &mxc_ccm->cscmr2); |
| 469 | |
Pardeep Kumar Singla | 0b87ba0 | 2013-07-25 12:12:14 -0500 | [diff] [blame] | 470 | reg = readl(&mxc_ccm->chsccdr); |
| 471 | reg |= (CHSCCDR_CLK_SEL_LDB_DI0 |
| 472 | << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); |
Fabio Estevam | 9e642cd | 2013-09-04 15:12:38 -0300 | [diff] [blame] | 473 | reg |= (CHSCCDR_CLK_SEL_LDB_DI0 |
| 474 | << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET); |
Pardeep Kumar Singla | 0b87ba0 | 2013-07-25 12:12:14 -0500 | [diff] [blame] | 475 | writel(reg, &mxc_ccm->chsccdr); |
Fabio Estevam | 9e642cd | 2013-09-04 15:12:38 -0300 | [diff] [blame] | 476 | |
| 477 | reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
| 478 | | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
| 479 | | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
| 480 | | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
| 481 | | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
| 482 | | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
| 483 | | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
| 484 | | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED |
| 485 | | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0; |
| 486 | writel(reg, &iomux->gpr[2]); |
| 487 | |
| 488 | reg = readl(&iomux->gpr[3]); |
| 489 | reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
| 490 | | IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) |
| 491 | | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 |
| 492 | << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET); |
| 493 | writel(reg, &iomux->gpr[3]); |
Pardeep Kumar Singla | 0b87ba0 | 2013-07-25 12:12:14 -0500 | [diff] [blame] | 494 | } |
| 495 | #endif /* CONFIG_VIDEO_IPUV3 */ |
| 496 | |
| 497 | /* |
| 498 | * Do not overwrite the console |
| 499 | * Use always serial for U-Boot console |
| 500 | */ |
| 501 | int overwrite_console(void) |
| 502 | { |
| 503 | return 1; |
| 504 | } |
| 505 | |
Fabio Estevam | 2ebe246 | 2012-09-18 17:24:23 +0000 | [diff] [blame] | 506 | int board_eth_init(bd_t *bis) |
| 507 | { |
Fabio Estevam | 2ebe246 | 2012-09-18 17:24:23 +0000 | [diff] [blame] | 508 | setup_iomux_enet(); |
Marek Vasut | 0e99f01 | 2014-03-23 22:45:41 +0100 | [diff] [blame] | 509 | setup_pcie(); |
Fabio Estevam | 2ebe246 | 2012-09-18 17:24:23 +0000 | [diff] [blame] | 510 | |
Fabio Estevam | fa3ae40 | 2014-01-04 17:36:32 -0200 | [diff] [blame] | 511 | return cpu_eth_init(bis); |
Fabio Estevam | 2ebe246 | 2012-09-18 17:24:23 +0000 | [diff] [blame] | 512 | } |
| 513 | |
Peng Fan | c9498fa | 2014-12-02 09:55:27 +0800 | [diff] [blame] | 514 | #ifdef CONFIG_USB_EHCI_MX6 |
| 515 | #define USB_OTHERREGS_OFFSET 0x800 |
| 516 | #define UCTRL_PWR_POL (1 << 9) |
| 517 | |
| 518 | static iomux_v3_cfg_t const usb_otg_pads[] = { |
| 519 | MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 520 | MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 521 | }; |
| 522 | |
| 523 | static iomux_v3_cfg_t const usb_hc1_pads[] = { |
| 524 | MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 525 | }; |
| 526 | |
| 527 | static void setup_usb(void) |
| 528 | { |
| 529 | imx_iomux_v3_setup_multiple_pads(usb_otg_pads, |
| 530 | ARRAY_SIZE(usb_otg_pads)); |
| 531 | |
| 532 | /* |
| 533 | * set daisy chain for otg_pin_id on 6q. |
| 534 | * for 6dl, this bit is reserved |
| 535 | */ |
| 536 | imx_iomux_set_gpr_register(1, 13, 1, 0); |
| 537 | |
| 538 | imx_iomux_v3_setup_multiple_pads(usb_hc1_pads, |
| 539 | ARRAY_SIZE(usb_hc1_pads)); |
| 540 | } |
| 541 | |
| 542 | int board_ehci_hcd_init(int port) |
| 543 | { |
| 544 | u32 *usbnc_usb_ctrl; |
| 545 | |
| 546 | if (port > 1) |
| 547 | return -EINVAL; |
| 548 | |
| 549 | usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + |
| 550 | port * 4); |
| 551 | |
| 552 | setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); |
| 553 | |
| 554 | return 0; |
| 555 | } |
| 556 | |
| 557 | int board_ehci_power(int port, int on) |
| 558 | { |
| 559 | switch (port) { |
| 560 | case 0: |
| 561 | break; |
| 562 | case 1: |
| 563 | if (on) |
| 564 | gpio_direction_output(IMX_GPIO_NR(1, 29), 1); |
| 565 | else |
| 566 | gpio_direction_output(IMX_GPIO_NR(1, 29), 0); |
| 567 | break; |
| 568 | default: |
| 569 | printf("MXC USB port %d not yet supported\n", port); |
| 570 | return -EINVAL; |
| 571 | } |
| 572 | |
| 573 | return 0; |
| 574 | } |
| 575 | #endif |
| 576 | |
Fabio Estevam | 77e6289 | 2012-09-13 03:18:20 +0000 | [diff] [blame] | 577 | int board_early_init_f(void) |
| 578 | { |
| 579 | setup_iomux_uart(); |
Pardeep Kumar Singla | 0b87ba0 | 2013-07-25 12:12:14 -0500 | [diff] [blame] | 580 | #if defined(CONFIG_VIDEO_IPUV3) |
| 581 | setup_display(); |
| 582 | #endif |
Fabio Estevam | 77e6289 | 2012-09-13 03:18:20 +0000 | [diff] [blame] | 583 | |
| 584 | return 0; |
| 585 | } |
| 586 | |
| 587 | int board_init(void) |
| 588 | { |
| 589 | /* address of boot parameters */ |
| 590 | gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
| 591 | |
Fabio Estevam | d82dad4 | 2013-11-08 16:20:54 -0200 | [diff] [blame] | 592 | #ifdef CONFIG_MXC_SPI |
| 593 | setup_spi(); |
| 594 | #endif |
Fabio Estevam | ba92ad6 | 2014-05-09 13:15:42 -0300 | [diff] [blame] | 595 | setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); |
| 596 | |
Peng Fan | c9498fa | 2014-12-02 09:55:27 +0800 | [diff] [blame] | 597 | #ifdef CONFIG_USB_EHCI_MX6 |
| 598 | setup_usb(); |
| 599 | #endif |
| 600 | |
Fabio Estevam | ba92ad6 | 2014-05-09 13:15:42 -0300 | [diff] [blame] | 601 | return 0; |
| 602 | } |
| 603 | |
Ye.Li | 75e02f9 | 2014-11-06 16:29:00 +0800 | [diff] [blame] | 604 | int power_init_board(void) |
Fabio Estevam | ba92ad6 | 2014-05-09 13:15:42 -0300 | [diff] [blame] | 605 | { |
| 606 | struct pmic *p; |
Fabio Estevam | effbec1 | 2015-07-21 20:02:49 -0300 | [diff] [blame] | 607 | unsigned int reg; |
| 608 | int ret; |
Fabio Estevam | ba92ad6 | 2014-05-09 13:15:42 -0300 | [diff] [blame] | 609 | |
Ye.Li | 75e02f9 | 2014-11-06 16:29:00 +0800 | [diff] [blame] | 610 | p = pfuze_common_init(I2C_PMIC); |
| 611 | if (!p) |
| 612 | return -ENODEV; |
Fabio Estevam | ba92ad6 | 2014-05-09 13:15:42 -0300 | [diff] [blame] | 613 | |
Peng Fan | e5bcd4d | 2015-01-27 10:14:04 +0800 | [diff] [blame] | 614 | ret = pfuze_mode_init(p, APS_PFM); |
| 615 | if (ret < 0) |
| 616 | return ret; |
| 617 | |
Fabio Estevam | ba92ad6 | 2014-05-09 13:15:42 -0300 | [diff] [blame] | 618 | /* Increase VGEN3 from 2.5 to 2.8V */ |
| 619 | pmic_reg_read(p, PFUZE100_VGEN3VOL, ®); |
Ye.Li | 75e02f9 | 2014-11-06 16:29:00 +0800 | [diff] [blame] | 620 | reg &= ~LDO_VOL_MASK; |
| 621 | reg |= LDOB_2_80V; |
Fabio Estevam | ba92ad6 | 2014-05-09 13:15:42 -0300 | [diff] [blame] | 622 | pmic_reg_write(p, PFUZE100_VGEN3VOL, reg); |
| 623 | |
| 624 | /* Increase VGEN5 from 2.8 to 3V */ |
| 625 | pmic_reg_read(p, PFUZE100_VGEN5VOL, ®); |
Ye.Li | 75e02f9 | 2014-11-06 16:29:00 +0800 | [diff] [blame] | 626 | reg &= ~LDO_VOL_MASK; |
| 627 | reg |= LDOB_3_00V; |
Fabio Estevam | ba92ad6 | 2014-05-09 13:15:42 -0300 | [diff] [blame] | 628 | pmic_reg_write(p, PFUZE100_VGEN5VOL, reg); |
| 629 | |
Fabio Estevam | 77e6289 | 2012-09-13 03:18:20 +0000 | [diff] [blame] | 630 | return 0; |
| 631 | } |
| 632 | |
Nikita Kiryanov | 00cd738 | 2014-08-20 15:08:50 +0300 | [diff] [blame] | 633 | #ifdef CONFIG_MXC_SPI |
| 634 | int board_spi_cs_gpio(unsigned bus, unsigned cs) |
| 635 | { |
| 636 | return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1; |
| 637 | } |
| 638 | #endif |
| 639 | |
Otavio Salvador | 5286337 | 2013-03-16 08:05:07 +0000 | [diff] [blame] | 640 | #ifdef CONFIG_CMD_BMODE |
| 641 | static const struct boot_mode board_boot_modes[] = { |
| 642 | /* 4 bit bus width */ |
| 643 | {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, |
| 644 | {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, |
| 645 | /* 8 bit bus width */ |
Ye Li | 4ea4a9b | 2016-01-30 11:53:42 +0800 | [diff] [blame] | 646 | {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)}, |
Otavio Salvador | 5286337 | 2013-03-16 08:05:07 +0000 | [diff] [blame] | 647 | {NULL, 0}, |
| 648 | }; |
| 649 | #endif |
| 650 | |
| 651 | int board_late_init(void) |
| 652 | { |
| 653 | #ifdef CONFIG_CMD_BMODE |
| 654 | add_board_boot_modes(board_boot_modes); |
| 655 | #endif |
Peng Fan | 04321fc | 2015-07-11 11:38:46 +0800 | [diff] [blame] | 656 | |
| 657 | #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
| 658 | setenv("board_name", "SABRESD"); |
| 659 | |
Peng Fan | e27c4db | 2015-10-15 18:05:59 +0800 | [diff] [blame] | 660 | if (is_mx6dqp()) |
| 661 | setenv("board_rev", "MX6QP"); |
| 662 | else if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) |
Peng Fan | 04321fc | 2015-07-11 11:38:46 +0800 | [diff] [blame] | 663 | setenv("board_rev", "MX6Q"); |
| 664 | else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO)) |
| 665 | setenv("board_rev", "MX6DL"); |
| 666 | #endif |
| 667 | |
Otavio Salvador | 5286337 | 2013-03-16 08:05:07 +0000 | [diff] [blame] | 668 | return 0; |
| 669 | } |
| 670 | |
Fabio Estevam | 77e6289 | 2012-09-13 03:18:20 +0000 | [diff] [blame] | 671 | int checkboard(void) |
| 672 | { |
Pierre Aubert | ec10aed | 2013-06-04 09:00:15 +0200 | [diff] [blame] | 673 | puts("Board: MX6-SabreSD\n"); |
Fabio Estevam | 77e6289 | 2012-09-13 03:18:20 +0000 | [diff] [blame] | 674 | return 0; |
| 675 | } |
John Tobias | 0749155 | 2014-11-12 14:27:45 -0800 | [diff] [blame] | 676 | |
| 677 | #ifdef CONFIG_SPL_BUILD |
| 678 | #include <spl.h> |
| 679 | #include <libfdt.h> |
| 680 | |
| 681 | const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { |
| 682 | .dram_sdclk_0 = 0x00020030, |
| 683 | .dram_sdclk_1 = 0x00020030, |
| 684 | .dram_cas = 0x00020030, |
| 685 | .dram_ras = 0x00020030, |
| 686 | .dram_reset = 0x00020030, |
| 687 | .dram_sdcke0 = 0x00003000, |
| 688 | .dram_sdcke1 = 0x00003000, |
| 689 | .dram_sdba2 = 0x00000000, |
| 690 | .dram_sdodt0 = 0x00003030, |
| 691 | .dram_sdodt1 = 0x00003030, |
| 692 | .dram_sdqs0 = 0x00000030, |
| 693 | .dram_sdqs1 = 0x00000030, |
| 694 | .dram_sdqs2 = 0x00000030, |
| 695 | .dram_sdqs3 = 0x00000030, |
| 696 | .dram_sdqs4 = 0x00000030, |
| 697 | .dram_sdqs5 = 0x00000030, |
| 698 | .dram_sdqs6 = 0x00000030, |
| 699 | .dram_sdqs7 = 0x00000030, |
| 700 | .dram_dqm0 = 0x00020030, |
| 701 | .dram_dqm1 = 0x00020030, |
| 702 | .dram_dqm2 = 0x00020030, |
| 703 | .dram_dqm3 = 0x00020030, |
| 704 | .dram_dqm4 = 0x00020030, |
| 705 | .dram_dqm5 = 0x00020030, |
| 706 | .dram_dqm6 = 0x00020030, |
| 707 | .dram_dqm7 = 0x00020030, |
| 708 | }; |
| 709 | |
Peng Fan | e27c4db | 2015-10-15 18:05:59 +0800 | [diff] [blame] | 710 | const struct mx6dq_iomux_ddr_regs mx6dqp_ddr_ioregs = { |
| 711 | .dram_sdclk_0 = 0x00000030, |
| 712 | .dram_sdclk_1 = 0x00000030, |
| 713 | .dram_cas = 0x00000030, |
| 714 | .dram_ras = 0x00000030, |
| 715 | .dram_reset = 0x00000030, |
| 716 | .dram_sdcke0 = 0x00003000, |
| 717 | .dram_sdcke1 = 0x00003000, |
| 718 | .dram_sdba2 = 0x00000000, |
| 719 | .dram_sdodt0 = 0x00003030, |
| 720 | .dram_sdodt1 = 0x00003030, |
| 721 | .dram_sdqs0 = 0x00000030, |
| 722 | .dram_sdqs1 = 0x00000030, |
| 723 | .dram_sdqs2 = 0x00000030, |
| 724 | .dram_sdqs3 = 0x00000030, |
| 725 | .dram_sdqs4 = 0x00000030, |
| 726 | .dram_sdqs5 = 0x00000030, |
| 727 | .dram_sdqs6 = 0x00000030, |
| 728 | .dram_sdqs7 = 0x00000030, |
| 729 | .dram_dqm0 = 0x00000030, |
| 730 | .dram_dqm1 = 0x00000030, |
| 731 | .dram_dqm2 = 0x00000030, |
| 732 | .dram_dqm3 = 0x00000030, |
| 733 | .dram_dqm4 = 0x00000030, |
| 734 | .dram_dqm5 = 0x00000030, |
| 735 | .dram_dqm6 = 0x00000030, |
| 736 | .dram_dqm7 = 0x00000030, |
| 737 | }; |
| 738 | |
John Tobias | 0749155 | 2014-11-12 14:27:45 -0800 | [diff] [blame] | 739 | const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { |
| 740 | .grp_ddr_type = 0x000C0000, |
| 741 | .grp_ddrmode_ctl = 0x00020000, |
| 742 | .grp_ddrpke = 0x00000000, |
| 743 | .grp_addds = 0x00000030, |
| 744 | .grp_ctlds = 0x00000030, |
| 745 | .grp_ddrmode = 0x00020000, |
| 746 | .grp_b0ds = 0x00000030, |
| 747 | .grp_b1ds = 0x00000030, |
| 748 | .grp_b2ds = 0x00000030, |
| 749 | .grp_b3ds = 0x00000030, |
| 750 | .grp_b4ds = 0x00000030, |
| 751 | .grp_b5ds = 0x00000030, |
| 752 | .grp_b6ds = 0x00000030, |
| 753 | .grp_b7ds = 0x00000030, |
| 754 | }; |
| 755 | |
| 756 | const struct mx6_mmdc_calibration mx6_mmcd_calib = { |
| 757 | .p0_mpwldectrl0 = 0x001F001F, |
| 758 | .p0_mpwldectrl1 = 0x001F001F, |
| 759 | .p1_mpwldectrl0 = 0x00440044, |
| 760 | .p1_mpwldectrl1 = 0x00440044, |
| 761 | .p0_mpdgctrl0 = 0x434B0350, |
| 762 | .p0_mpdgctrl1 = 0x034C0359, |
| 763 | .p1_mpdgctrl0 = 0x434B0350, |
| 764 | .p1_mpdgctrl1 = 0x03650348, |
| 765 | .p0_mprddlctl = 0x4436383B, |
| 766 | .p1_mprddlctl = 0x39393341, |
| 767 | .p0_mpwrdlctl = 0x35373933, |
| 768 | .p1_mpwrdlctl = 0x48254A36, |
| 769 | }; |
| 770 | |
Peng Fan | e27c4db | 2015-10-15 18:05:59 +0800 | [diff] [blame] | 771 | const struct mx6_mmdc_calibration mx6dqp_mmcd_calib = { |
| 772 | .p0_mpwldectrl0 = 0x001B001E, |
| 773 | .p0_mpwldectrl1 = 0x002E0029, |
| 774 | .p1_mpwldectrl0 = 0x001B002A, |
| 775 | .p1_mpwldectrl1 = 0x0019002C, |
| 776 | .p0_mpdgctrl0 = 0x43240334, |
| 777 | .p0_mpdgctrl1 = 0x0324031A, |
| 778 | .p1_mpdgctrl0 = 0x43340344, |
| 779 | .p1_mpdgctrl1 = 0x03280276, |
| 780 | .p0_mprddlctl = 0x44383A3E, |
| 781 | .p1_mprddlctl = 0x3C3C3846, |
| 782 | .p0_mpwrdlctl = 0x2E303230, |
| 783 | .p1_mpwrdlctl = 0x38283E34, |
| 784 | }; |
| 785 | |
Fabio Estevam | 2f3641c | 2015-04-16 22:11:47 -0300 | [diff] [blame] | 786 | /* MT41K128M16JT-125 */ |
John Tobias | 0749155 | 2014-11-12 14:27:45 -0800 | [diff] [blame] | 787 | static struct mx6_ddr3_cfg mem_ddr = { |
| 788 | .mem_speed = 1600, |
Fabio Estevam | 2f3641c | 2015-04-16 22:11:47 -0300 | [diff] [blame] | 789 | .density = 2, |
| 790 | .width = 16, |
John Tobias | 0749155 | 2014-11-12 14:27:45 -0800 | [diff] [blame] | 791 | .banks = 8, |
| 792 | .rowaddr = 14, |
| 793 | .coladdr = 10, |
| 794 | .pagesz = 2, |
| 795 | .trcd = 1375, |
| 796 | .trcmin = 4875, |
| 797 | .trasmin = 3500, |
| 798 | }; |
| 799 | |
Fabio Estevam | c6ecd0b | 2014-11-14 09:36:59 -0200 | [diff] [blame] | 800 | static void ccgr_init(void) |
| 801 | { |
| 802 | struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| 803 | |
| 804 | writel(0x00C03F3F, &ccm->CCGR0); |
| 805 | writel(0x0030FC03, &ccm->CCGR1); |
| 806 | writel(0x0FFFC000, &ccm->CCGR2); |
| 807 | writel(0x3FF00000, &ccm->CCGR3); |
| 808 | writel(0x00FFF300, &ccm->CCGR4); |
| 809 | writel(0x0F0000C3, &ccm->CCGR5); |
| 810 | writel(0x000003FF, &ccm->CCGR6); |
| 811 | } |
| 812 | |
| 813 | static void gpr_init(void) |
| 814 | { |
| 815 | struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; |
| 816 | |
| 817 | /* enable AXI cache for VDOA/VPU/IPU */ |
| 818 | writel(0xF00000CF, &iomux->gpr[4]); |
Peng Fan | e27c4db | 2015-10-15 18:05:59 +0800 | [diff] [blame] | 819 | if (is_mx6dqp()) { |
| 820 | /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */ |
| 821 | writel(0x007F007F, &iomux->gpr[6]); |
| 822 | writel(0x007F007F, &iomux->gpr[7]); |
| 823 | } else { |
| 824 | /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ |
| 825 | writel(0x007F007F, &iomux->gpr[6]); |
| 826 | writel(0x007F007F, &iomux->gpr[7]); |
| 827 | } |
Fabio Estevam | c6ecd0b | 2014-11-14 09:36:59 -0200 | [diff] [blame] | 828 | } |
| 829 | |
John Tobias | 0749155 | 2014-11-12 14:27:45 -0800 | [diff] [blame] | 830 | /* |
Fabio Estevam | 44606e2 | 2014-11-15 14:57:52 -0200 | [diff] [blame] | 831 | * This section requires the differentiation between iMX6 Sabre boards, but |
| 832 | * for now, it will configure only for the mx6q variant. |
John Tobias | 0749155 | 2014-11-12 14:27:45 -0800 | [diff] [blame] | 833 | */ |
| 834 | static void spl_dram_init(void) |
| 835 | { |
| 836 | struct mx6_ddr_sysinfo sysinfo = { |
| 837 | /* width of data bus:0=16,1=32,2=64 */ |
Fabio Estevam | 2f3641c | 2015-04-16 22:11:47 -0300 | [diff] [blame] | 838 | .dsize = 2, |
John Tobias | 0749155 | 2014-11-12 14:27:45 -0800 | [diff] [blame] | 839 | /* config for full 4GB range so that get_mem_size() works */ |
| 840 | .cs_density = 32, /* 32Gb per CS */ |
| 841 | /* single chip select */ |
| 842 | .ncs = 1, |
| 843 | .cs1_mirror = 0, |
| 844 | .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ |
John Tobias | 0749155 | 2014-11-12 14:27:45 -0800 | [diff] [blame] | 845 | .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ |
John Tobias | 0749155 | 2014-11-12 14:27:45 -0800 | [diff] [blame] | 846 | .walat = 1, /* Write additional latency */ |
| 847 | .ralat = 5, /* Read additional latency */ |
| 848 | .mif3_mode = 3, /* Command prediction working mode */ |
| 849 | .bi_on = 1, /* Bank interleaving enabled */ |
| 850 | .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ |
| 851 | .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ |
Peng Fan | 77e8695 | 2015-08-17 16:11:03 +0800 | [diff] [blame] | 852 | .ddr_type = DDR_TYPE_DDR3, |
John Tobias | 0749155 | 2014-11-12 14:27:45 -0800 | [diff] [blame] | 853 | }; |
| 854 | |
Peng Fan | e27c4db | 2015-10-15 18:05:59 +0800 | [diff] [blame] | 855 | if (is_mx6dqp()) { |
| 856 | mx6dq_dram_iocfg(64, &mx6dqp_ddr_ioregs, &mx6_grp_ioregs); |
| 857 | mx6_dram_cfg(&sysinfo, &mx6dqp_mmcd_calib, &mem_ddr); |
| 858 | } else { |
| 859 | mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); |
| 860 | mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); |
| 861 | } |
John Tobias | 0749155 | 2014-11-12 14:27:45 -0800 | [diff] [blame] | 862 | } |
| 863 | |
| 864 | void board_init_f(ulong dummy) |
| 865 | { |
| 866 | /* setup AIPS and disable watchdog */ |
| 867 | arch_cpu_init(); |
| 868 | |
Fabio Estevam | c6ecd0b | 2014-11-14 09:36:59 -0200 | [diff] [blame] | 869 | ccgr_init(); |
| 870 | gpr_init(); |
| 871 | |
John Tobias | 0749155 | 2014-11-12 14:27:45 -0800 | [diff] [blame] | 872 | /* iomux and setup of i2c */ |
| 873 | board_early_init_f(); |
| 874 | |
| 875 | /* setup GP timer */ |
| 876 | timer_init(); |
| 877 | |
| 878 | /* UART clocks enabled and gd valid - init serial console */ |
| 879 | preloader_console_init(); |
| 880 | |
| 881 | /* DDR initialization */ |
| 882 | spl_dram_init(); |
| 883 | |
| 884 | /* Clear the BSS. */ |
| 885 | memset(__bss_start, 0, __bss_end - __bss_start); |
| 886 | |
| 887 | /* load/boot image from boot device */ |
| 888 | board_init_r(NULL, 0); |
| 889 | } |
John Tobias | 0749155 | 2014-11-12 14:27:45 -0800 | [diff] [blame] | 890 | #endif |