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git01.mediatek.com / filogic / uboot / 45dbaf2b9e1e0ca0e8231154c579ffb0208166ab / . / board / Marvell / sheevaplug / sheevaplug.c
blob: 547126af8f049bd66693c2ee383d4bb2d04f1ae2 [file] [log] [blame]
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]1/*
2 * (C) Copyright 2009
3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 */
24
25#include <common.h>
26#include <miiphy.h>
27#include <asm/arch/kirkwood.h>
28#include <asm/arch/mpp.h>
29#include "sheevaplug.h"
30
31DECLARE_GLOBAL_DATA_PTR;
32
33int board_init(void)
34{
35 /*
36 * default gpio configuration
37 * There are maximum 64 gpios controlled through 2 sets of registers
38 * the below configuration configures mainly initial LED status
39 */
40 kw_config_gpio(SHEEVAPLUG_OE_VAL_LOW,
41 SHEEVAPLUG_OE_VAL_HIGH,
42 SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH);
43
44 /* Multi-Purpose Pins Functionality configuration */
45 u32 kwmpp_config[] = {
46 MPP0_NF_IO2,
47 MPP1_NF_IO3,
48 MPP2_NF_IO4,
49 MPP3_NF_IO5,
50 MPP4_NF_IO6,
51 MPP5_NF_IO7,
52 MPP6_SYSRST_OUTn,
53 MPP7_GPO,
54 MPP8_UART0_RTS,
55 MPP9_UART0_CTS,
56 MPP10_UART0_TXD,
57 MPP11_UART0_RXD,
58 MPP12_SD_CLK,
59 MPP13_SD_CMD,
60 MPP14_SD_D0,
61 MPP15_SD_D1,
62 MPP16_SD_D2,
63 MPP17_SD_D3,
64 MPP18_NF_IO0,
65 MPP19_NF_IO1,
66 MPP20_GPIO,
67 MPP21_GPIO,
68 MPP22_GPIO,
69 MPP23_GPIO,
70 MPP24_GPIO,
71 MPP25_GPIO,
72 MPP26_GPIO,
73 MPP27_GPIO,
74 MPP28_GPIO,
75 MPP29_TSMP9,
76 MPP30_GPIO,
77 MPP31_GPIO,
78 MPP32_GPIO,
79 MPP33_GPIO,
80 MPP34_GPIO,
81 MPP35_GPIO,
82 MPP36_GPIO,
83 MPP37_GPIO,
84 MPP38_GPIO,
85 MPP39_GPIO,
86 MPP40_GPIO,
87 MPP41_GPIO,
88 MPP42_GPIO,
89 MPP43_GPIO,
90 MPP44_GPIO,
91 MPP45_GPIO,
92 MPP46_GPIO,
93 MPP47_GPIO,
94 MPP48_GPIO,
95 MPP49_GPIO,
96 0
97 };
98 kirkwood_mpp_conf(kwmpp_config);
99
100 /*
101 * arch number of board
102 */
103 gd->bd->bi_arch_number = MACH_TYPE_SHEEVAPLUG;
104
105 /* adress of boot parameters */
106 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
107
108 return 0;
109}
110
111int dram_init(void)
112{
113 int i;
114
115 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
116 gd->bd->bi_dram[i].start = kw_sdram_bar(i);
117 gd->bd->bi_dram[i].size = kw_sdram_bs(i);
118 }
119 return 0;
120}
121
122#ifdef CONFIG_RESET_PHY_R
123/* Configure and enable MV88E1116 PHY */
124void reset_phy(void)
125{
126 u16 reg;
127 u16 devadr;
128 char *name = "egiga0";
129
130 if (miiphy_set_current_dev(name))
131 return;
132
133 /* command to read PHY dev address */
134 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
135 printf("Err..%s could not read PHY dev address\n",
136 __FUNCTION__);
137 return;
138 }
139
140 /*
141 * Enable RGMII delay on Tx and Rx for CPU port
142 * Ref: sec 4.7.2 of chip datasheet
143 */
144 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
145 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
146 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
147 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
148 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
149
150 /* reset the phy */
151 miiphy_reset(name, devadr);
152
153 printf("88E1116 Initialized on %s\n", name);
154}
155#endif /* CONFIG_RESET_PHY_R */