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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Wenyou Yang8c772bd2016-07-20 17:55:12 +08002/*
3 * Copyright (C) 2016 Atmel Corporation
4 * Wenyou.Yang <wenyou.yang@atmel.com>
Wenyou Yang8c772bd2016-07-20 17:55:12 +08005 */
6
7#include <common.h>
8#include <clk-uclass.h>
Simon Glass11c89f32017-05-17 17:18:03 -06009#include <dm.h>
Wenyou Yang8c772bd2016-07-20 17:55:12 +080010#include <linux/io.h>
11#include <mach/at91_pmc.h>
12#include "pmc.h"
13
14DECLARE_GLOBAL_DATA_PTR;
15
16static int plla_clk_enable(struct clk *clk)
17{
18 struct pmc_platdata *plat = dev_get_platdata(clk->dev);
19 struct at91_pmc *pmc = plat->reg_base;
20
21 if (readl(&pmc->sr) & AT91_PMC_LOCKA)
22 return 0;
23
24 return -EINVAL;
25}
26
27static ulong plla_clk_get_rate(struct clk *clk)
28{
29 return gd->arch.plla_rate_hz;
30}
31
32static struct clk_ops plla_clk_ops = {
33 .enable = plla_clk_enable,
34 .get_rate = plla_clk_get_rate,
35};
36
37static int plla_clk_probe(struct udevice *dev)
38{
39 return at91_pmc_core_probe(dev);
40}
41
42static const struct udevice_id plla_clk_match[] = {
43 { .compatible = "atmel,sama5d3-clk-pll" },
44 {}
45};
46
47U_BOOT_DRIVER(at91_plla_clk) = {
48 .name = "at91-plla-clk",
49 .id = UCLASS_CLK,
50 .of_match = plla_clk_match,
51 .probe = plla_clk_probe,
52 .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
53 .ops = &plla_clk_ops,
54};