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git01.mediatek.com / filogic / uboot / 45be8102524a661c3e876aa347b4f2b43fcf2bcb / . / arch / arm / dts / zynqmp-sc-vn-p-b2197-00-revA.dtso
blob: 5333767361f5bd07b5cf3dbad0249d2f2371b97a [file] [log] [blame]
Michal Simekeaa6f3d2023-09-27 11:53:34 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx ZynqMP VN-P-B2197-00 (Tenzing2)
4 *
5 * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
6 *
7 * Michal Simek <michal.simek@amd.com>
8 */
9
10#include <dt-bindings/gpio/gpio.h>
11
12/dts-v1/;
13/plugin/;
14
15&{/} {
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 compatible = "xlnx,zynqmp-sc-vn-p-b2197-revA",
20 "xlnx,zynqmp-sc-vn-p-b2197", "xlnx,zynqmp";
21
22 aliases {
23 nvmem1 = &x_prc_eeprom;
24 };
25
26 ina226-u1700 {
27 compatible = "iio-hwmon";
28 io-channels = <&vcc_ram_ina 0>, <&vcc_ram_ina 1>, <&vcc_ram_ina 2>;
29 };
30 ina226-u1732 {
31 compatible = "iio-hwmon";
32 io-channels = <&vcc_lpd_ina 0>, <&vcc_lpd_ina 1>, <&vcc_lpd_ina 2>;
33 };
34 ina226-u1733 {
35 compatible = "iio-hwmon";
36 io-channels = <&vccaux_ina 0>, <&vccaux_ina 1>, <&vccaux_ina 2>;
37 };
38 ina226-u1736 {
39 compatible = "iio-hwmon";
40 io-channels = <&vccaux_lpd_ina 0>, <&vccaux_lpd_ina 1>, <&vccaux_lpd_ina 2>;
41 };
42 ina226-u1737 {
43 compatible = "iio-hwmon";
44 io-channels = <&vcco_500_ina 0>, <&vcco_500_ina 1>, <&vcco_500_ina 2>;
45 };
46 ina226-u1739 {
47 compatible = "iio-hwmon";
48 io-channels = <&vcco_501_ina 0>, <&vcco_501_ina 1>, <&vcco_501_ina 2>;
49 };
50 ina226-u1741 {
51 compatible = "iio-hwmon";
52 io-channels = <&vcco_502_ina 0>, <&vcco_502_ina 1>, <&vcco_502_ina 2>;
53 };
54 ina226-u1743 {
55 compatible = "iio-hwmon";
56 io-channels = <&vcco_503_ina 0>, <&vcco_503_ina 1>, <&vcco_503_ina 2>;
57 };
58 ina226-u1745 {
59 compatible = "iio-hwmon";
60 io-channels = <&vcco_700_ina 0>, <&vcco_700_ina 1>, <&vcco_700_ina 2>;
61 };
62 ina226-u1747 {
63 compatible = "iio-hwmon";
64 io-channels = <&vcco_706_ina 0>, <&vcco_706_ina 1>, <&vcco_706_ina 2>;
65 };
66 ina226-u1750 {
67 compatible = "iio-hwmon";
68 io-channels = <&gtyp_avcc_ina 0>, <&gtyp_avcc_ina 1>, <&gtyp_avcc_ina 2>;
69 };
70 ina226-u1752 {
71 compatible = "iio-hwmon";
72 io-channels = <&gtyp_avtt_ina 0>, <&gtyp_avtt_ina 1>, <&gtyp_avtt_ina 2>;
73 };
74 ina226-u1754 {
75 compatible = "iio-hwmon";
76 io-channels = <&gtyp_avccaux_ina 0>, <&gtyp_avccaux_ina 1>, <&gtyp_avccaux_ina 2>;
77 };
78 ina226-u1756 {
79 compatible = "iio-hwmon";
80 io-channels = <&gtm_avcc_ina 0>, <&gtm_avcc_ina 1>, <&gtm_avcc_ina 2>;
81 };
82 ina226-u1758 {
83 compatible = "iio-hwmon";
84 io-channels = <&gtm_avtt_ina 0>, <&gtm_avtt_ina 1>, <&gtm_avtt_ina 2>;
85 };
86 ina226-u1760 {
87 compatible = "iio-hwmon";
88 io-channels = <&gtm_avccaux_ina 0>, <&gtm_avccaux_ina 1>, <&gtm_avccaux_ina 2>;
89 };
90
91 /* sc_vpk180_axi_iic_0_0: i2c@80050000 - UNUSED NOW */ /* SI5332 */
92
93 /* Connect to J212G pin G29/G30 - sysmon connector */
94 /* sc_vpk180_axi_iic_1_0: i2c@80060000 */ /* SYSMON */
95
96 /* FIXME Fan control via u1702 - max6643 and mux via J1703 - not SW controllable - via EMIO */
97};
98
99&i2c1 {
100 #address-cells = <1>;
101 #size-cells = <0>;
102
103 /* u97 eeprom at 0x54 described in sc-revB - WP protection via BOARD_EEPROM_WP - J1801 */
104 /* DC/SE eeprom at 0x52 */
105 x_prc_eeprom: eeprom@52 { /* u4 - DC card identification - possible WP */
106 compatible = "atmel,24c02";
107 reg = <0x52>;
108 bootph-all;
109 };
110
111 x_prc_tca9534: gpio@22 { /* u5 */
112 compatible = "nxp,pca9534";
113 reg = <0x22>;
114 gpio-controller; /* IRQ not connected */
115 #gpio-cells = <2>;
116 gpio-line-names = "xprc_sw_1", "xprc_sw_2", "xprc_sw_3", "xprc_sw_4",
117 "", "", "", "";
118 gtr-sel0 {
119 gpio-hog;
120 gpios = <0 0>;
121 input; /* FIXME add meaning */
122 line-name = "xprc_sw_1";
123 };
124 gtr-sel1 {
125 gpio-hog;
126 gpios = <1 0>;
127 input; /* FIXME add meaning */
128 line-name = "xprc_sw_1";
129 };
130 gtr-sel2 {
131 gpio-hog;
132 gpios = <2 0>;
133 input; /* FIXME add meaning */
134 line-name = "xprc_sw_1";
135 };
136 gtr-sel3 {
137 gpio-hog;
138 gpios = <3 0>;
139 input; /* FIXME add meaning */
140 line-name = "xprc_sw_1";
141 };
142 };
143
144 /* FMC eeproms at 0x50/0x51 */
145 /* via j3/j5 to 0x68 to u32/9FGV1006C
146
147 /* i2c_main_1 - u147 - j157 - disable translation, add 8 */
148 /* J1 - OE for u43@55 + 8 - 161,132813MHz - QSFP56G_0 */
149 qsfp56g_0_clk: clock-controller@5d {
150 compatible = "renesas,proxo-xp";
151 reg = <0x5d>;
152 #clock-cells = <0>;
153 clock-output-names = "qsfp56g_0_clk";
154 };
155
156 /* J2 - OE for u41@57 + 8 - 322,265625MHz - QSFP56G_1 */
157 qsfp56g_1_clk: clock-controller@5f {
158 compatible = "renesas,proxo-xp";
159 reg = <0x5f>;
160 #clock-cells = <0>;
161 clock-output-names = "qsfp56g_1_clk";
162 };
163
164 /* J81 - OE for u115@50 + 8 - 320MHz - LPDDR5_C0 */
165 lpddr5_c0_clk: clock-controller@58 {
166 compatible = "renesas,proxo-xp";
167 reg = <0x58>;
168 #clock-cells = <0>;
169 clock-output-names = "lpddr5_c0_clk";
170 };
171
172 /* i2c_main_2 - u148 - j122 - disable translation, add 9 */
173 /* J112 - OE for u63@50 + 9 - 320MHz - LPDDR5_C2 */
174 lpddr5_c2_clk: clock-controller@59 {
175 compatible = "renesas,proxo-xp";
176 reg = <0x59>;
177 #clock-cells = <0>;
178 clock-output-names = "lpddr5_c2_clk";
179 };
180
181 /* i2c_main_3 - u149 - j154 - disable translation, add 6 */
182 /* J78 - OE for u116@50 + 6 - 320MHz - DDR5_UDIMM */
183 ddr5_udimm_clk: clock-controller@56 {
184 compatible = "renesas,proxo-xp";
185 reg = <0x56>;
186 #clock-cells = <0>;
187 clock-output-names = "ddr5_udimm_clk";
188 };
189
190 /* i2c_main_4 - u150 - j146 - disable translation, add 5 */
191 /* J107 - OE for u39@50 + 5 - 33,3333MHz - PS_REFCLK */
192 ps_refclk: clock-controller@55 {
193 compatible = "renesas,proxo-xp";
194 reg = <0x55>;
195 #clock-cells = <0>;
196 clock-output-names = "ps_refclk";
197 };
198
199 /* i2c_main_5 - u1782 - j1798 - disable translation, add 7 */
200 /* J77 - OE for u1783@50 + 7 - 320MHz - DDR4 */
201 ddr4_clk: clock-controller@57 {
202 compatible = "renesas,proxo-xp";
203 reg = <0x57>;
204 #clock-cells = <0>;
205 clock-output-names = "ddr4_clk";
206 };
207
208 /* LTC4316 - not wired XORH/XORL - FIXME */
209 /* J3 gate - FIXME should be connected for SW handling */
210 /* i2c_main_1 bus */
211 i2c1_u32: clock-controller@68 {
212 compatible = "renesas,9fgv1006";
213 reg = <0x68>;
214 };
215
216 /* J71 - selection to LP_I2C_SCL_J or LP_I2C_PMC_SCL_J */
217 /* J70 - selection to LP_I2C_SDA_J or LP_I2C_PMC_SDA_J */
218 /* this should be SW controlable too */
219};
220
221&i2c0 {
222 #address-cells = <1>;
223 #size-cells = <0>;
224
225 /* Via j11/j12 can also go to u17/IML3112 - 1:2 multiplexer - also accessed from Versal NET */
226 /* Connection DDR5_UDIMM - SPD can be from 0x50-0x57 */
227 /* FIXME gpio should handle SYSCTLR_PMBUS_ALERT and also INA226_PMBUS_ALERT */
228
229 /* ina226_pmbus - J55 - disable INA226_PMBUS */
230 vcc_ram_ina: power-monitor@40 { /* u1700 */
231 compatible = "ti,ina226";
232 #io-channel-cells = <1>;
233 reg = <0x40>;
234 shunt-resistor = <1000>; /* R1996 */
235 };
236
237 vcc_lpd_ina: power-monitor@41 { /* u1732 */
238 compatible = "ti,ina226";
239 #io-channel-cells = <1>;
240 reg = <0x41>;
241 shunt-resistor = <1000>; /* R2017 */
242 };
243
244 vccaux_ina: power-monitor@42 { /* u1733 */
245 compatible = "ti,ina226";
246 #io-channel-cells = <1>;
247 reg = <0x42>;
248 shunt-resistor = <1000>; /* R2037 */
249 };
250
251 vccaux_lpd_ina: power-monitor@43 { /* u1736 */
252 compatible = "ti,ina226";
253 #io-channel-cells = <1>;
254 reg = <0x43>;
255 shunt-resistor = <1000>; /* R2057 */
256 };
257
258 vcco_500_ina: power-monitor@44 { /* u1737 */
259 compatible = "ti,ina226";
260 #io-channel-cells = <1>;
261 reg = <0x44>;
262 shunt-resistor = <1000>; /* R2069 */
263 };
264
265 vcco_501_ina: power-monitor@45 { /* u1739 */
266 compatible = "ti,ina226";
267 #io-channel-cells = <1>;
268 reg = <0x45>;
269 shunt-resistor = <1000>; /* R2089 */
270 };
271
272 vcco_502_ina: power-monitor@46 { /* u1741 */
273 compatible = "ti,ina226";
274 #io-channel-cells = <1>;
275 reg = <0x46>;
276 shunt-resistor = <1000>; /* R2108 */
277 };
278
279 vcco_503_ina: power-monitor@47 { /* u1743 */
280 compatible = "ti,ina226";
281 #io-channel-cells = <1>;
282 reg = <0x47>;
283 shunt-resistor = <1000>; /* R2127 */
284 };
285
286 vcco_700_ina: power-monitor@48 { /* u1745 */
287 compatible = "ti,ina226";
288 #io-channel-cells = <1>;
289 reg = <0x48>;
290 shunt-resistor = <1000>; /* R2154 */
291 };
292
293 vcco_706_ina: power-monitor@49 { /* u1747 */
294 compatible = "ti,ina226";
295 #io-channel-cells = <1>;
296 reg = <0x49>;
297 shunt-resistor = <1000>; /* R2175 */
298 };
299
300 gtyp_avcc_ina: power-monitor@4a { /* u1750 */
301 compatible = "ti,ina226";
302 #io-channel-cells = <1>;
303 reg = <0x4a>;
304 shunt-resistor = <1000>; /* R2195 */
305 };
306
307 gtyp_avtt_ina: power-monitor@4b { /* u1752 */
308 compatible = "ti,ina226";
309 #io-channel-cells = <1>;
310 reg = <0x4b>;
311 shunt-resistor = <1000>; /* R2215 */
312 };
313
314 gtyp_avccaux_ina: power-monitor@4c { /* u1754 */
315 compatible = "ti,ina226";
316 #io-channel-cells = <1>;
317 reg = <0x4c>;
318 shunt-resistor = <5000>; /* R2235 */
319 };
320
321 gtm_avcc_ina: power-monitor@4d { /* u1756 */
322 compatible = "ti,ina226";
323 #io-channel-cells = <1>;
324 reg = <0x4d>;
325 shunt-resistor = <1000>; /* R2256 */
326 };
327
328 gtm_avtt_ina: power-monitor@4e { /* u1758 */
329 compatible = "ti,ina226";
330 #io-channel-cells = <1>;
331 reg = <0x4e>;
332 shunt-resistor = <1000>; /* R2276 */
333 };
334
335 gtm_avccaux_ina: power-monitor@4f { /* u1760 */
336 compatible = "ti,ina226";
337 #io-channel-cells = <1>;
338 reg = <0x4f>;
339 shunt-resistor = <5000>; /* R2296 */
340 };
341
342 /* pmbus - J50 - disable main PMBUS - also going to j132 */
343 vcc_ram: regulator@a { /* u1730 */
344 compatible = "ti,tps544b25";
345 reg = <0xa>;
346 };
347
348 vcc_lpd: regulator@b { /* u1731 */
349 compatible = "ti,tps544b25";
350 reg = <0xb>;
351 };
352
353 vccaux: regulator@1a { /* u1734 */
354 compatible = "ti,tps544b25";
355 reg = <0x1a>;
356 };
357
358 vcco_503: regulator@12 { /* u1744 */
359 compatible = "ti,tps546b24a";
360 reg = <0x12>;
361 };
362
363 vcco_700: regulator@16 { /* u1746 */
364 compatible = "ti,tps544b25";
365 reg = <0x16>;
366 };
367
368 vcco_706: regulator@17 { /* u1748 */
369 compatible = "ti,tps544b25";
370 reg = <0x17>;
371 };
372
373 gtm_avcc: regulator@23 { /* u1755 */
374 compatible = "ti,tps544b25";
375 reg = <0x23>;
376 };
377
378 gtm_avtt: regulator@24 { /* u1757 */
379 compatible = "ti,tps544b25";
380 reg = <0x24>;
381 };
382
383 gtm_avccaux: regulator@25 { /* u1759 */
384 compatible = "ti,tps544b25";
385 reg = <0x25>;
386 };
387
388 util_1v8: regulator@15 { /* u1765 */
389 compatible = "ti,tps544b25";
390 reg = <0x15>;
391 };
392
393 ucd90320: power-sequencer@73 { /* u1768 */
394 compatible = "ti,ucd90320";
395 reg = <0x73>;
396 };
397
398 /* EXT_PMBUS main - J10 - disable extended PMBUS */
399 vccint: tps53681@60 { /* u1712 - J1770 reset jumper */
400 compatible = "ti,tps53681", "ti,tps53679";
401 reg = <0x60>;
402 /* vccint, vcc_cpm5n */
403 };
404
405 vcc_io_soc: tps53681@61 { /* u1721 - J1772 reset jumper */
406 compatible = "ti,tps53681", "ti,tps53679";
407 reg = <0x61>;
408 /* vcc_io_soc, vcc_fpd */
409 };
410
411 vccaux_lpd: regulator@d { /* u1735 */
412 compatible = "ti,tps544b25";
413 reg = <0xd>;
414 };
415
416 vcco_500: regulator@13 { /* u1738 */
417 compatible = "ti,tps546b24a";
418 reg = <0x13>;
419 };
420
421 vcco_501: regulator@10 { /* u1740 */
422 compatible = "ti,tps546b24a";
423 reg = <0x10>;
424 };
425
426 vcco_502: regulator@11 { /* u1742 */
427 compatible = "ti,tps546b24a";
428 reg = <0x11>;
429 };
430
431 gtyp_avcc: regulator@20 { /* u1749 */
432 compatible = "ti,tps544b25";
433 reg = <0x20>;
434 };
435
436 gtyp_avtt: regulator@21 { /* u1751 */
437 compatible = "ti,tps544b25";
438 reg = <0x21>;
439 };
440
441 gtyp_avccaux: regulator@22 { /* u1753 */
442 compatible = "ti,tps544b25";
443 reg = <0x22>;
444 };
445
446 lp5_vdd1_1v8: regulator@e { /* u1761 - FIXME no ina226 */
447 compatible = "ti,tps544b25";
448 reg = <0xe>;
449 };
450
451 lp5_vdd2_1v05: regulator@f { /* u1762 - FIXME no ina226 */
452 compatible = "ti,tps544b25";
453 reg = <0xf>;
454 };
455
456 lp5_vddq_0v5: regulator@14 { /* u1763 - FIXME no ina226 */
457 compatible = "ti,tps546b24a";
458 reg = <0x14>;
459 };
460};