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git01.mediatek.com / filogic / uboot / 45b66c4d617d941f2118d19e21a9c603cc7a0d37 / . / arch / arm / dts / zynqmp-e-a2197-00-revA.dts
blob: 7bcdbdfdbb065b770f1718d4093c23cb465ee9c0 [file] [log] [blame]
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx Versal a2197 RevA System Controller
4 *
Saeed Nowshadi35a2cd62021-03-22 11:58:38 -0700[diff] [blame]5 * (C) Copyright 2019 - 2021, Xilinx, Inc.
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9/dts-v1/;
10
11#include "zynqmp.dtsi"
12#include "zynqmp-clk-ccf.dtsi"
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/phy/phy.h>
15
16/ {
17 model = "Versal System Controller on a2197 Eval board RevA"; /* VCK190/VMK180 */
18 compatible = "xlnx,zynqmp-e-a2197-00-revA", "xlnx,zynqmp-a2197-revA",
19 "xlnx,zynqmp-a2197", "xlnx,zynqmp";
20
21 aliases {
22 ethernet0 = &gem0;
23 gpio0 = &gpio;
24 i2c0 = &i2c0;
25 i2c1 = &i2c1;
26 mmc0 = &sdhci1;
27 rtc0 = &rtc;
28 serial0 = &uart0;
29 serial1 = &dcc;
30 };
31
32 chosen {
33 bootargs = "earlycon";
34 stdout-path = "serial0:115200n8";
35 xlnx,eeprom = <&eeprom>;
36 };
37
38 memory@0 {
39 device_type = "memory";
40 reg = <0x0 0x0 0x0 0x80000000>;
41 };
42
43 ina226-vccint {
44 compatible = "iio-hwmon";
45 io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
46 };
47 ina226-vcc-soc {
48 compatible = "iio-hwmon";
49 io-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>;
50 };
51 ina226-vcc-pmc {
52 compatible = "iio-hwmon";
53 io-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>;
54 };
55 ina226-vcc-ram {
56 compatible = "iio-hwmon";
57 io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
58 };
59 ina226-vcc-pslp {
60 compatible = "iio-hwmon";
61 io-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>;
62 };
63 ina226-vcc-psfp {
64 compatible = "iio-hwmon";
65 io-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>;
66 };
67 ina226-vccaux {
68 compatible = "iio-hwmon";
69 io-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>;
70 };
71 ina226-vccaux-pmc {
72 compatible = "iio-hwmon";
73 io-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>;
74 };
75 ina226-vcco-500 {
76 compatible = "iio-hwmon";
77 io-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>;
78 };
79 ina226-vcco-501 {
80 compatible = "iio-hwmon";
81 io-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>;
82 };
83 ina226-vcco-502 {
84 compatible = "iio-hwmon";
85 io-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>;
86 };
87 ina226-vcco-503 {
88 compatible = "iio-hwmon";
89 io-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>;
90 };
91 ina226-vcc-1v8 {
92 compatible = "iio-hwmon";
93 io-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>;
94 };
95 ina226-vcc-3v3 {
96 compatible = "iio-hwmon";
97 io-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>;
98 };
99 ina226-vcc-1v2-ddr4 {
100 compatible = "iio-hwmon";
101 io-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>;
102 };
103 ina226-vcc-1v1-lp4 {
104 compatible = "iio-hwmon";
105 io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
106 };
107 ina226-vadj-fmc {
108 compatible = "iio-hwmon";
109 io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
110 };
111 ina226-mgtyavcc {
112 compatible = "iio-hwmon";
113 io-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>;
114 };
115 ina226-mgtyavtt {
116 compatible = "iio-hwmon";
117 io-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>;
118 };
119 ina226-mgtyvccaux {
120 compatible = "iio-hwmon";
121 io-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>;
122 };
123};
124
125&uart0 { /* uart0 MIO38-39 */
126 status = "okay";
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]127};
128
129&sdhci1 { /* sd1 MIO45-51 cd in place */
130 status = "okay";
131 no-1-8-v;
132 disable-wp;
Michal Simek3b662642020-07-22 17:42:43 +0200[diff] [blame]133 xlnx,mio-bank = <1>;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]134};
135
136&gem0 {
137 status = "okay";
138 phy-handle = <&phy0>;
139 phy-mode = "sgmii";
140 is-internal-pcspma;
141 phy0: ethernet-phy@0 { /* u131 M88E1512 */
142 reg = <0>;
143 };
144};
145
146&gpio {
147 status = "okay";
148 gpio-line-names = "", "", "", "", "", /* 0 - 4 */
149 "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */
150 "DC_SYS_CTRL3", "ZU4_TRIGGER", "SYSCTLR_PB", "", "", /* 10 - 14 */
151 "", "", "", "", "", /* 15 - 19 */
152 "", "", "", "", "", /* 20 - 24 */
153 "", "", "", "", "", /* 25 - 29 */
154 "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
155 "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
156 "", "", "ETH_RESET_B", "", "", /* 40 - 44 */
157 "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
158 "SD1_CMD", "SD1_CLK", "", "", "", /* 50 - 54 */
159 "", "", "", "", "", /* 55 - 59 */
160 "", "", "", "", "", /* 60 - 64 */
161 "", "", "", "", "", /* 65 - 69 */
162 "", "", "", "", "", /* 70 - 74 */
163 "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
Saeed Nowshadi893180e2020-03-27 08:12:20 -0700[diff] [blame]164 "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
Saeed Nowshadi342c3cd2021-04-13 16:01:42 -0700[diff] [blame]165 "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "", /* 80 - 84 */
166 "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */
167 "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */
168 "SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]169 "", "", "", "", "", /* 100 - 104 */
170 "", "", "", "", "", /* 105 - 109 */
171 "", "", "", "", "", /* 110 - 114 */
172 "", "", "", "", "", /* 115 - 119 */
173 "", "", "", "", "", /* 120 - 124 */
174 "", "", "", "", "", /* 125 - 129 */
Saeed Nowshadi342c3cd2021-04-13 16:01:42 -0700[diff] [blame]175 "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "", "", "", /* 130 - 134 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]176 "", "", "", "", "", /* 135 - 139 */
Saeed Nowshadi342c3cd2021-04-13 16:01:42 -0700[diff] [blame]177 "PMBUS_ALERT", "", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */
178 "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]179 "", "", "", "", "", /* 150 - 154 */
180 "", "", "", "", "", /* 155 - 159 */
181 "", "", "", "", "", /* 160 - 164 */
182 "", "", "", "", "", /* 165 - 169 */
183 "", "", "", ""; /* 170 - 174 */
184};
185
186&i2c0 { /* MIO 34-35 - can't stay here */
187 status = "okay";
188 clock-frequency = <400000>;
189 i2c-mux@74 { /* u33 */
190 compatible = "nxp,pca9548";
191 #address-cells = <1>;
192 #size-cells = <0>;
193 reg = <0x74>;
194 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
195 i2c@0 { /* PMBUS */
196 #address-cells = <1>;
197 #size-cells = <0>;
198 reg = <0>;
199 /* u152 IR35215 0x16/0x46 vcc_soc */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]200 /* u179 ir38164 0x19/0x49 vcco_500 */
201 /* u181 ir38164 0x1a/0x4a vcco_501 */
202 /* u183 ir38164 0x1b/0x4b vcco_502 */
203 /* u185 ir38164 0x1e/0x4e vadj_fmc */
204 /* u187 ir38164 0x1F/0x4f mgtyavcc */
205 /* u189 ir38164 0x20/0x50 mgtyavtt */
206 /* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */
207 /* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */
Michal Simek3514e4e2020-03-30 11:35:38 +0200[diff] [blame]208
209 irps5401_47: irps5401@47 { /* IRPS5401 - u160 */
210 compatible = "infineon,irps5401";
211 reg = <0x47>; /* pmbus / i2c 0x17 */
212 };
213 irps5401_4c: irps5401@4c { /* IRPS5401 - u167 */
214 compatible = "infineon,irps5401";
215 reg = <0x4c>; /* pmbus / i2c 0x1c */
216 };
217 irps5401_4d: irps5401@4d { /* IRPS5401 - u175 */
218 compatible = "infineon,irps5401";
219 reg = <0x4d>; /* pmbus / i2c 0x1d */
220 };
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]221 };
222 i2c@1 { /* PMBUS1_INA226 */
223 #address-cells = <1>;
224 #size-cells = <0>;
225 reg = <1>;
226 /* FIXME check alerts coming to SC */
227 vccint: ina226@40 { /* u65 */
228 compatible = "ti,ina226";
229 #io-channel-cells = <1>;
230 label = "ina226-vccint";
231 reg = <0x40>;
Saeed Nowshadi34cd5f82020-08-03 23:24:05 -0700[diff] [blame]232 shunt-resistor = <500>; /* R440 */
233 /* 0.80V @ 32A 1 of 6 Phases*/
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]234 };
235 vcc_soc: ina226@41 { /* u161 */
236 compatible = "ti,ina226";
237 #io-channel-cells = <1>;
238 label = "ina226-vcc-soc";
239 reg = <0x41>;
Saeed Nowshadi34cd5f82020-08-03 23:24:05 -0700[diff] [blame]240 shunt-resistor = <500>; /* R1702 */
241 /* 0.80V @ 18A */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]242 };
243 vcc_pmc: ina226@42 { /* u163 */
244 compatible = "ti,ina226";
245 #io-channel-cells = <1>;
246 label = "ina226-vcc-pmc";
247 reg = <0x42>;
248 shunt-resistor = <5000>; /* R1214 */
249 /* 0.78V @ 500mA */
250 };
251 vcc_ram: ina226@43 { /* u162 */
252 compatible = "ti,ina226";
253 #io-channel-cells = <1>;
254 label = "ina226-vcc-ram";
255 reg = <0x43>;
256 shunt-resistor = <5000>; /* r1221 */
257 /* 0.78V @ 4A */
258 };
259 vcc_pslp: ina226@44 { /* u165 */
260 compatible = "ti,ina226";
261 #io-channel-cells = <1>;
262 label = "ina226-vcc-pslp";
263 reg = <0x44>;
264 shunt-resistor = <5000>; /* R1216 */
265 /* 0.78V @ 1A */
266 };
267 vcc_psfp: ina226@45 { /* u164 */
268 compatible = "ti,ina226";
269 #io-channel-cells = <1>;
270 label = "ina226-vcc-psfp";
271 reg = <0x45>;
272 shunt-resistor = <5000>; /* R1219 */
273 /* 0.78V @ 2A */
274 };
275 };
276 i2c@2 { /* PCIE_CLK */
277 #address-cells = <1>;
278 #size-cells = <0>;
279 reg = <2>;
280 clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 */
281 #clock-cells = <1>; /* author David Cater <david.cater@idt.com>*/
282 compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */
283 reg = <0xd8>;
284 /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */
285 /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */
286 };
287 };
288 i2c@3 { /* PMBUS2_INA226 */
289 #address-cells = <1>;
290 #size-cells = <0>;
291 reg = <3>;
292 /* FIXME check alerts coming to SC */
293 vccaux: ina226@40 { /* u166 */
294 compatible = "ti,ina226";
295 #io-channel-cells = <1>;
296 label = "ina226-vccaux";
297 reg = <0x40>;
298 shunt-resistor = <5000>; /* R382 */
299 /* 1.5V @ 3A */
300 };
301 vccaux_pmc: ina226@41 { /* u168 */
302 compatible = "ti,ina226";
303 #io-channel-cells = <1>;
304 label = "ina226-vccaux-pmc";
305 reg = <0x41>;
306 shunt-resistor = <5000>; /* R1246 */
307 /* 1.5V @ 500mA */
308 };
309 vcco_500: ina226@42 { /* u178 */
310 compatible = "ti,ina226";
311 #io-channel-cells = <1>;
312 label = "ina226-vcco-500";
313 reg = <0x42>;
314 shunt-resistor = <2000>; /* R1300 */
315 /* 3.3V @ 5A */
316 };
317 vcco_501: ina226@43 { /* u180 */
318 compatible = "ti,ina226";
319 #io-channel-cells = <1>;
320 label = "ina226-vcco-501";
321 reg = <0x43>;
322 shunt-resistor = <2000>; /* R1313 */
323 /* 3.3V @ 5A */
324 };
325 vcco_502: ina226@44 { /* u182 */
326 compatible = "ti,ina226";
327 #io-channel-cells = <1>;
328 label = "ina226-vcco-502";
329 reg = <0x44>;
330 shunt-resistor = <2000>; /* R1330 */
331 /* 3.3V @ 5A */
332 };
333 vcco_503: ina226@45 { /* u172 */
334 compatible = "ti,ina226";
335 #io-channel-cells = <1>;
336 label = "ina226-vcco-503";
337 reg = <0x45>;
338 shunt-resistor = <5000>; /* R1229 */
339 /* 1.8V @ 2A */
340 };
341 vcc_1v8: ina226@46 { /* u173 */
342 compatible = "ti,ina226";
343 #io-channel-cells = <1>;
344 label = "ina226-vcc-1v8";
345 reg = <0x46>;
346 shunt-resistor = <5000>; /* R400 */
347 /* 1.8V @ 6A */
348 };
349 vcc_3v3: ina226@47 { /* u174 */
350 compatible = "ti,ina226";
351 #io-channel-cells = <1>;
352 label = "ina226-vcc-3v3";
353 reg = <0x47>;
354 shunt-resistor = <5000>; /* R1232 */
355 /* 3.3V @ 500mA */
356 };
357 vcc_1v2_ddr4: ina226@48 { /* u176 */
358 compatible = "ti,ina226";
359 #io-channel-cells = <1>;
360 label = "ina226-vcc-1v2-ddr4";
361 reg = <0x48>;
362 shunt-resistor = <5000>; /* R1275 */
363 /* 1.2V @ 4A */
364 };
365 vcc1v1_lp4: ina226@49 { /* u177 */
366 compatible = "ti,ina226";
367 #io-channel-cells = <1>;
368 label = "ina226-vcc1v1-lp4";
369 reg = <0x49>;
370 shunt-resistor = <5000>; /* R1286 */
371 /* 1.1V @ 4A */
372 };
373 vadj_fmc: ina226@4a { /* u184 */
374 compatible = "ti,ina226";
375 #io-channel-cells = <1>;
376 label = "ina226-vadj-fmc";
377 reg = <0x4a>;
378 shunt-resistor = <2000>; /* R1350 */
379 /* 1.5V @ 10A */
380 };
381 mgtyavcc: ina226@4b { /* u186 */
382 compatible = "ti,ina226";
383 #io-channel-cells = <1>;
384 label = "ina226-mgtyavcc";
385 reg = <0x4b>;
386 shunt-resistor = <2000>; /* R1367 */
387 /* 0.88V @ 6A */
388 };
389 mgtyavtt: ina226@4c { /* u188 */
390 compatible = "ti,ina226";
391 #io-channel-cells = <1>;
392 label = "ina226-mgtyavtt";
393 reg = <0x4c>;
394 shunt-resistor = <2000>; /* R1384 */
395 /* 1.2V @ 10A */
396 };
397 mgtyvccaux: ina226@4d { /* u234 */
398 compatible = "ti,ina226";
399 #io-channel-cells = <1>;
400 label = "ina226-mgtyvccaux";
401 reg = <0x4d>;
402 shunt-resistor = <5000>; /* r1679 */
403 /* 1.5V @ 500mA */
404 };
405 };
406 i2c@4 { /* LP_I2C_SM */
407 #address-cells = <1>;
408 #size-cells = <0>;
409 reg = <4>;
410 /* FIXME wires ready but chip is missing */
411 };
412 i2c@5 { /* zSFP_SI570 */
413 #address-cells = <1>;
414 #size-cells = <0>;
415 reg = <5>;
416 si570_zsfp: clock-generator@5d { /* u192 */
417 #clock-cells = <0>;
418 compatible = "silabs,si570";
419 reg = <0x5d>;
420 temperature-stability = <50>;
421 factory-fout = <156250000>;
422 clock-frequency = <156250000>;
Saeed Nowshadi9a34a4b2020-03-04 10:21:34 -0800[diff] [blame]423 clock-output-names = "si570_zsfp_clk";
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]424 };
425 };
426 i2c@6 { /* USER_SI570_1 */
427 #address-cells = <1>;
428 #size-cells = <0>;
429 reg = <6>;
Saeed Nowshadi9a34a4b2020-03-04 10:21:34 -0800[diff] [blame]430 si570_user1: clock-generator@5d { /* u205 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]431 #clock-cells = <0>;
432 compatible = "silabs,si570";
433 reg = <0x5f>;
434 temperature-stability = <50>;
435 factory-fout = <100000000>;
436 clock-frequency = <100000000>;
437 clock-output-names = "si570_user1";
438 };
439
440 };
441 i2c@7 { /* USER_SI570_2 */
442 #address-cells = <1>;
443 #size-cells = <0>;
444 reg = <7>;
445 /* FIXME wires ready but chip is missing */
446 };
447 };
448};
449
450&i2c1 { /* i2c1 MIO 36-37 */
451 status = "okay";
452 clock-frequency = <400000>;
453
454 i2c-mux@74 { /* u35 */
455 compatible = "nxp,pca9548";
456 #address-cells = <1>;
457 #size-cells = <0>;
458 reg = <0x74>;
Raviteja Narayanam574fa192021-04-01 07:14:10 -0600[diff] [blame]459 i2c-mux-idle-disconnect;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]460 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
461 dc_i2c: i2c@0 { /* DC_I2C */
462 #address-cells = <1>;
463 #size-cells = <0>;
464 reg = <0>;
465 /* Use for storing information about SC board */
466 eeprom: eeprom@54 { /* u34 - m24128 16kB */
467 compatible = "st,24c128", "atmel,24c128";
468 reg = <0x54>; /* 0x5c too */
469 };
470 si570_ref_clk: clock-generator@5d { /* u32 */
471 #clock-cells = <0>;
472 compatible = "silabs,si570";
473 reg = <0x5d>;
474 temperature-stability = <50>;
475 factory-fout = <33333333>;
476 clock-frequency = <33333333>;
477 clock-output-names = "ref_clk";
Michal Simekf86d2b52021-03-09 12:43:42 +0100[diff] [blame]478 silabs,skip-recall;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]479 };
480 /* and connector J212D */
481 };
482 fmc1: i2c@1 { /* FMCP1_IIC */
483 #address-cells = <1>;
484 #size-cells = <0>;
485 reg = <1>;
486 /* FIXME connection to Samtec J51C */
487 /* expected eeprom 0x50 FMC cards */
488 };
489 fmc2: i2c@2 { /* FMCP2_IIC */
490 #address-cells = <1>;
491 #size-cells = <0>;
492 reg = <2>;
493 /* FIXME connection to Samtec J53C */
494 /* expected eeprom 0x50 FMC cards */
495 };
496 i2c@3 { /* DDR4_DIMM1 */
497 #address-cells = <1>;
498 #size-cells = <0>;
499 reg = <3>;
500 si570_ddr_dimm1: clock-generator@60 { /* u2 */
501 #clock-cells = <0>;
502 compatible = "silabs,si570";
503 reg = <0x60>;
504 temperature-stability = <50>;
505 factory-fout = <200000000>;
506 clock-frequency = <200000000>;
507 clock-output-names = "si570_ddrdimm1_clk";
Saeed Nowshadi35a2cd62021-03-22 11:58:38 -0700[diff] [blame]508 silabs,skip-recall;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]509 };
510 };
511 i2c@4 { /* LPDDR4_SI570_CLK2 */
512 #address-cells = <1>;
513 #size-cells = <0>;
514 reg = <4>;
Saeed Nowshadi9a34a4b2020-03-04 10:21:34 -0800[diff] [blame]515 si570_lpddr4clk2: clock-generator@60 { /* u3 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]516 #clock-cells = <0>;
517 compatible = "silabs,si570";
518 reg = <0x60>;
519 temperature-stability = <50>;
520 factory-fout = <200000000>;
521 clock-frequency = <200000000>;
522 clock-output-names = "si570_lpddr4_clk2";
523 };
524 };
525 i2c@5 { /* LPDDR4_SI570_CLK1 */
526 #address-cells = <1>;
527 #size-cells = <0>;
528 reg = <5>;
Saeed Nowshadi9a34a4b2020-03-04 10:21:34 -0800[diff] [blame]529 si570_lpddr4clk1: clock-generator@60 { /* u4 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]530 #clock-cells = <0>;
531 compatible = "silabs,si570";
532 reg = <0x60>;
533 temperature-stability = <50>;
534 factory-fout = <200000000>;
535 clock-frequency = <200000000>;
536 clock-output-names = "si570_lpddr4_clk1";
537 };
538 };
539 i2c@6 { /* HSDP_SI570 */
540 #address-cells = <1>;
541 #size-cells = <0>;
542 reg = <6>;
543 si570_hsdp: clock-generator@5d { /* u5 */
544 #clock-cells = <0>;
545 compatible = "silabs,si570";
546 reg = <0x5d>;
547 temperature-stability = <50>;
548 factory-fout = <156250000>;
549 clock-frequency = <156250000>;
550 clock-output-names = "si570_hsdp_clk";
551 };
552 };
553 i2c@7 { /* 8A34001 - U219B and J310 connector */
554 #address-cells = <1>;
555 #size-cells = <0>;
556 reg = <7>;
557 };
558 };
Saeed Nowshadic06192e2020-08-03 23:24:04 -0700[diff] [blame]559 i2c-mux@75 { /* u214 */
560 compatible = "nxp,pca9548";
561 #address-cells = <1>;
562 #size-cells = <0>;
563 reg = <0x75>;
Raviteja Narayanam574fa192021-04-01 07:14:10 -0600[diff] [blame]564 i2c-mux-idle-disconnect;
Saeed Nowshadic06192e2020-08-03 23:24:04 -0700[diff] [blame]565 i2c@0 { /* SFP0_IIC */
566 #address-cells = <1>;
567 #size-cells = <0>;
568 reg = <0>;
569 /* SFP0 */
570 };
571 i2c@1 { /* SFP1_IIC */
572 #address-cells = <1>;
573 #size-cells = <0>;
574 reg = <1>;
575 /* SFP1 */
576 };
577 i2c@2 { /* QSFP1_I2C */
578 #address-cells = <1>;
579 #size-cells = <0>;
580 reg = <2>;
581 /* QSFP1 */
582 };
583 /* 3 - 7 unused */
584 };
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]585};
586
587&xilinx_ams {
588 status = "okay";
589};
590
591&ams_ps {
592 status = "okay";
593};
594
595&ams_pl {
596 status = "okay";
597};