blob: 4ea2300f4b7ff420ae7dd0a3d29275c029d602fc [file] [log] [blame]
Mike Frysingercc244082008-10-12 21:25:33 -04001/*
2 * U-boot - Configuration file for BF538F EZ-Kit Lite board
3 */
4
5#ifndef __CONFIG_BF538F_EZKIT_H__
6#define __CONFIG_BF538F_EZKIT_H__
7
Mike Frysinger18a407c2009-04-24 17:22:40 -04008#include <asm/config-pre.h>
Mike Frysingercc244082008-10-12 21:25:33 -04009
10
11/*
12 * Processor Settings
13 */
14#define CONFIG_BFIN_CPU bf538-0.4
15#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
16
17
18/*
19 * Clock Settings
20 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
21 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
22 */
23/* CONFIG_CLKIN_HZ is any value in Hz */
24#define CONFIG_CLKIN_HZ 25000000
25/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
26/* 1 = CLKIN / 2 */
27#define CONFIG_CLKIN_HALF 0
28/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
29/* 1 = bypass PLL */
30#define CONFIG_PLL_BYPASS 0
31/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
32/* Values can range from 0-63 (where 0 means 64) */
33#define CONFIG_VCO_MULT 21
34/* CCLK_DIV controls the core clock divider */
35/* Values can be 1, 2, 4, or 8 ONLY */
36#define CONFIG_CCLK_DIV 1
37/* SCLK_DIV controls the system clock divider */
38/* Values can range from 1-15 */
39#define CONFIG_SCLK_DIV 4
40
41
42/*
43 * Memory Settings
44 */
45#define CONFIG_MEM_ADD_WDTH 10
46#define CONFIG_MEM_SIZE 64
47
48#define CONFIG_EBIU_SDRRC_VAL (0x03F6)
49#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | PSS | TWR_2 | TRCD_3 | TRP_3 | TRAS_6 | PASR_ALL | CL_3)
50
51#define CONFIG_EBIU_AMGCTL_VAL (CDPRIO | AMBEN_ALL | AMCKEN)
52#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
53#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
54
55#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
56#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
57
58
59/*
60 * Network Settings
61 */
62#define ADI_CMDS_NETWORK 1
Ben Warren0fd6aae2009-10-04 22:37:03 -070063#define CONFIG_NET_MULTI
64#define CONFIG_SMC91111 1
Mike Frysingercc244082008-10-12 21:25:33 -040065#define CONFIG_SMC91111_BASE 0x20310300
66#define CONFIG_HOSTNAME bf538f-ezkit
67/* Uncomment next line to use fixed MAC address */
68/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
69
70
71/*
72 * Flash Settings
73 */
74#define CONFIG_FLASH_CFI_DRIVER
75#define CONFIG_SYS_FLASH_BASE 0x20000000
76#define CONFIG_SYS_FLASH_CFI
77#define CONFIG_SYS_FLASH_PROTECTION
78#define CONFIG_SYS_MAX_FLASH_BANKS 1
79#define CONFIG_SYS_MAX_FLASH_SECT 71
80
81
82/*
83 * SPI Settings
84 */
85#define CONFIG_BFIN_SPI
86#define CONFIG_ENV_SPI_MAX_HZ 30000000
Mike Frysinger9a4406462009-06-14 22:29:35 -040087#define CONFIG_SF_DEFAULT_SPEED 30000000
Mike Frysingercc244082008-10-12 21:25:33 -040088#define CONFIG_SPI_FLASH
89#define CONFIG_SPI_FLASH_ATMEL
90#define CONFIG_SPI_FLASH_SPANSION
91#define CONFIG_SPI_FLASH_STMICRO
92#define CONFIG_SPI_FLASH_WINBOND
93
94
95/*
96 * Env Storage Settings
97 */
98#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
99#define CONFIG_ENV_IS_IN_SPI_FLASH
100#define CONFIG_ENV_OFFSET 0x4000
101#define CONFIG_ENV_SIZE 0x2000
102#define CONFIG_ENV_SECT_SIZE 0x2000
103#else
104#define CONFIG_ENV_IS_IN_FLASH
105#define CONFIG_ENV_OFFSET 0x4000
106#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
107#define CONFIG_ENV_SIZE 0x2000
108#define CONFIG_ENV_SECT_SIZE 0x2000
109#endif
110#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
111#define ENV_IS_EMBEDDED
112#else
Mike Frysinger45b57bd2009-07-21 22:17:36 -0400113#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
Mike Frysingercc244082008-10-12 21:25:33 -0400114#endif
Mike Frysinger37f48702009-06-14 06:29:07 -0400115#ifdef ENV_IS_EMBEDDED
116/* WARNING - the following is hand-optimized to fit within
117 * the sector before the environment sector. If it throws
118 * an error during compilation remove an object here to get
119 * it linked after the configuration sector.
120 */
121# define LDS_BOARD_TEXT \
122 cpu/blackfin/traps.o (.text .text.*); \
123 cpu/blackfin/interrupt.o (.text .text.*); \
124 cpu/blackfin/serial.o (.text .text.*); \
125 common/dlmalloc.o (.text .text.*); \
126 lib_generic/crc32.o (.text .text.*); \
127 . = DEFINED(env_offset) ? env_offset : .; \
128 common/env_embedded.o (.text .text.*);
129#endif
Mike Frysingercc244082008-10-12 21:25:33 -0400130
131
132/*
133 * I2C Settings
134 */
135#define CONFIG_BFIN_TWI_I2C 1
136#define CONFIG_HARD_I2C 1
137#define CONFIG_SYS_I2C_SPEED 50000
138#define CONFIG_SYS_I2C_SLAVE 0
139
140
141/*
142 * Misc Settings
143 */
144#define CONFIG_RTC_BFIN
145#define CONFIG_UART_CONSOLE 0
146
147
148/*
149 * Pull in common ADI header for remaining command/environment setup
150 */
151#include <configs/bfin_adi_common.h>
152
Mike Frysingercc244082008-10-12 21:25:33 -0400153#endif