| Heiko Schocher | 420cd0a | 2011-09-14 19:44:00 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 DENX Software Engineering GmbH |
| 3 | * Heiko Schocher <hs@denx.de> |
| 4 | * |
| Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| Heiko Schocher | 420cd0a | 2011-09-14 19:44:00 +0000 | [diff] [blame] | 6 | */ |
| 7 | #ifndef _TIMER_DEFS_H_ |
| 8 | #define _TIMER_DEFS_H_ |
| 9 | |
| 10 | struct davinci_timer { |
| 11 | u_int32_t pid12; |
| 12 | u_int32_t emumgt; |
| 13 | u_int32_t na1; |
| 14 | u_int32_t na2; |
| 15 | u_int32_t tim12; |
| 16 | u_int32_t tim34; |
| 17 | u_int32_t prd12; |
| 18 | u_int32_t prd34; |
| 19 | u_int32_t tcr; |
| 20 | u_int32_t tgcr; |
| 21 | u_int32_t wdtcr; |
| 22 | }; |
| 23 | |
| Heiko Schocher | 507dfab | 2012-01-14 21:43:04 +0000 | [diff] [blame] | 24 | #define DV_TIMER_TCR_ENAMODE_MASK 3 |
| 25 | |
| 26 | #define DV_TIMER_TCR_ENAMODE12_SHIFT 6 |
| 27 | #define DV_TIMER_TCR_CLKSRC12_SHIFT 8 |
| 28 | #define DV_TIMER_TCR_READRSTMODE12_SHIFT 10 |
| 29 | #define DV_TIMER_TCR_CAPMODE12_SHIFT 11 |
| 30 | #define DV_TIMER_TCR_CAPVTMODE12_SHIFT 12 |
| 31 | #define DV_TIMER_TCR_ENAMODE34_SHIFT 22 |
| 32 | #define DV_TIMER_TCR_CLKSRC34_SHIFT 24 |
| 33 | #define DV_TIMER_TCR_READRSTMODE34_SHIFT 26 |
| 34 | #define DV_TIMER_TCR_CAPMODE34_SHIFT 27 |
| 35 | #define DV_TIMER_TCR_CAPEVTMODE12_SHIFT 28 |
| 36 | |
| Heiko Schocher | f15223f | 2012-01-14 21:42:46 +0000 | [diff] [blame] | 37 | #define DV_WDT_ENABLE_SYS_RESET 0x00020000 |
| 38 | #define DV_WDT_TRIGGER_SYS_RESET 0x00020002 |
| 39 | |
| Heiko Schocher | a2cddad | 2011-09-14 19:44:02 +0000 | [diff] [blame] | 40 | #ifdef CONFIG_HW_WATCHDOG |
| 41 | void davinci_hw_watchdog_enable(void); |
| 42 | void davinci_hw_watchdog_reset(void); |
| 43 | #endif |
| Heiko Schocher | 420cd0a | 2011-09-14 19:44:00 +0000 | [diff] [blame] | 44 | #endif /* _TIMER_DEFS_H_ */ |