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Nobuhiro Iwamatsu7e405632014-11-06 15:39:28 +09001/*
2 * include/configs/gose.h
3 *
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 *
6 * SPDX-License-Identifier: GPL-2.0
7 */
8
9#ifndef __GOSE_H
10#define __GOSE_H
11
12#undef DEBUG
13#define CONFIG_R8A7793
Nobuhiro Iwamatsu7c112732015-10-10 05:58:28 +090014#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Gose"
Nobuhiro Iwamatsu7e405632014-11-06 15:39:28 +090015
Nobuhiro Iwamatsub6169ac2014-11-10 14:34:07 +090016#include "rcar-gen2-common.h"
Nobuhiro Iwamatsu7e405632014-11-06 15:39:28 +090017
Nobuhiro Iwamatsu7c112732015-10-10 05:58:28 +090018#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
Nobuhiro Iwamatsu7e405632014-11-06 15:39:28 +090019#define CONFIG_SYS_TEXT_BASE 0x70000000
20#else
21#define CONFIG_SYS_TEXT_BASE 0xE6304000
22#endif
23
Nobuhiro Iwamatsu7e405632014-11-06 15:39:28 +090024/* STACK */
Nobuhiro Iwamatsu7c112732015-10-10 05:58:28 +090025#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
Nobuhiro Iwamatsu7e405632014-11-06 15:39:28 +090026#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
27#else
28#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC
29#endif
30
31#define STACK_AREA_SIZE 0xC000
32#define LOW_LEVEL_MERAM_STACK \
33 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
34
35/* MEMORY */
Nobuhiro Iwamatsub6169ac2014-11-10 14:34:07 +090036#define RCAR_GEN2_SDRAM_BASE 0x40000000
37#define RCAR_GEN2_SDRAM_SIZE 0x40000000
38#define RCAR_GEN2_UBOOT_SDRAM_SIZE 0x20000000
Nobuhiro Iwamatsu7e405632014-11-06 15:39:28 +090039
40/* SCIF */
41#define CONFIG_SCIF_CONSOLE
Nobuhiro Iwamatsu7e405632014-11-06 15:39:28 +090042
43/* FLASH */
Nobuhiro Iwamatsu7e405632014-11-06 15:39:28 +090044#define CONFIG_SPI
45#define CONFIG_SH_QSPI
Nobuhiro Iwamatsu7e405632014-11-06 15:39:28 +090046
Nobuhiro Iwamatsueef1f232014-11-06 15:42:24 +090047/* SH Ether */
Nobuhiro Iwamatsueef1f232014-11-06 15:42:24 +090048#define CONFIG_SH_ETHER
49#define CONFIG_SH_ETHER_USE_PORT 0
50#define CONFIG_SH_ETHER_PHY_ADDR 0x1
51#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
52#define CONFIG_SH_ETHER_CACHE_WRITEBACK
53#define CONFIG_SH_ETHER_CACHE_INVALIDATE
54#define CONFIG_PHYLIB
55#define CONFIG_PHY_MICREL
56#define CONFIG_BITBANGMII
57#define CONFIG_BITBANGMII_MULTI
58#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
59
Nobuhiro Iwamatsu7e405632014-11-06 15:39:28 +090060/* Board Clock */
61#define RMOBILE_XTAL_CLK 20000000u
62#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
63#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
Nobuhiro Iwamatsu7e405632014-11-06 15:39:28 +090064#define CONFIG_SYS_TMU_CLK_DIV 4
65
66/* I2C */
67#define CONFIG_SYS_I2C
68#define CONFIG_SYS_I2C_SH
69#define CONFIG_SYS_I2C_SLAVE 0x7F
70#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3
Nobuhiro Iwamatsu7e405632014-11-06 15:39:28 +090071#define CONFIG_SYS_I2C_SH_SPEED0 400000
Nobuhiro Iwamatsu7e405632014-11-06 15:39:28 +090072#define CONFIG_SYS_I2C_SH_SPEED1 400000
Nobuhiro Iwamatsu7e405632014-11-06 15:39:28 +090073#define CONFIG_SYS_I2C_SH_SPEED2 400000
74#define CONFIG_SH_I2C_DATA_HIGH 4
75#define CONFIG_SH_I2C_DATA_LOW 5
76#define CONFIG_SH_I2C_CLOCK 10000000
77
78#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
79
Nobuhiro Iwamatsu87adc0a2014-11-06 15:42:25 +090080/* USB */
Nobuhiro Iwamatsu87adc0a2014-11-06 15:42:25 +090081#define CONFIG_USB_EHCI
82#define CONFIG_USB_EHCI_RMOBILE
83#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
84
Nobuhiro Iwamatsue02f1742014-12-02 16:52:24 +090085/* Module stop status bits */
86/* INTC-RT */
87#define CONFIG_SMSTP0_ENA 0x00400000
88/* MSIF */
89#define CONFIG_SMSTP2_ENA 0x00002000
90/* INTC-SYS, IRQC */
91#define CONFIG_SMSTP4_ENA 0x00000180
92/* SCIF0 */
93#define CONFIG_SMSTP7_ENA 0x00200000
94
Nobuhiro Iwamatsu161af502014-11-12 11:29:39 +090095/* SDHI */
Nobuhiro Iwamatsu161af502014-11-12 11:29:39 +090096#define CONFIG_SH_SDHI_FREQ 97500000
97
Nobuhiro Iwamatsu7e405632014-11-06 15:39:28 +090098#endif /* __GOSE_H */