| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Device Tree Source for Sunplus SP7021 |
| 4 | * |
| 5 | * Copyright (C) 2021 Sunplus Technology Co. |
| 6 | */ |
| 7 | |
| 8 | #include "sunplus-sp7021.dtsi" |
| 9 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 10 | |
| 11 | / { |
| 12 | compatible = "sunplus,sp7021-achip", "sunplus,sp7021"; |
| 13 | model = "Sunplus SP7021 (CA7)"; |
| 14 | #address-cells = <1>; |
| 15 | #size-cells = <1>; |
| 16 | interrupt-parent = <&gic>; |
| 17 | |
| 18 | cpus { |
| 19 | #address-cells = <1>; |
| 20 | #size-cells = <0>; |
| 21 | |
| 22 | cpu0: cpu@0 { |
| 23 | compatible = "arm,cortex-a7"; |
| 24 | device_type = "cpu"; |
| 25 | reg = <0>; |
| 26 | clock-frequency = <931000000>; |
| 27 | }; |
| 28 | cpu1: cpu@1 { |
| 29 | compatible = "arm,cortex-a7"; |
| 30 | device_type = "cpu"; |
| 31 | reg = <1>; |
| 32 | clock-frequency = <931000000>; |
| 33 | }; |
| 34 | cpu2: cpu@2 { |
| 35 | compatible = "arm,cortex-a7"; |
| 36 | device_type = "cpu"; |
| 37 | reg = <2>; |
| 38 | clock-frequency = <931000000>; |
| 39 | }; |
| 40 | cpu3: cpu@3 { |
| 41 | compatible = "arm,cortex-a7"; |
| 42 | device_type = "cpu"; |
| 43 | reg = <3>; |
| 44 | clock-frequency = <931000000>; |
| 45 | }; |
| 46 | }; |
| 47 | |
| 48 | gic: interrupt-controller@9f101000 { |
| 49 | compatible = "arm,cortex-a7-gic"; |
| 50 | interrupt-controller; |
| 51 | #interrupt-cells = <3>; |
| 52 | reg = <0x9f101000 0x1000>, |
| 53 | <0x9f102000 0x2000>, |
| 54 | <0x9f104000 0x2000>, |
| 55 | <0x9f106000 0x2000>; |
| 56 | }; |
| 57 | |
| 58 | timer { |
| 59 | compatible = "arm,armv7-timer"; |
| 60 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 61 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 62 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 63 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
| 64 | clock-frequency = <XTAL>; |
| 65 | arm,cpu-registers-not-fw-configured; |
| 66 | }; |
| 67 | |
| 68 | arm-pmu { |
| 69 | compatible = "arm,cortex-a7-pmu"; |
| 70 | interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, |
| 71 | <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, |
| 72 | <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, |
| 73 | <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; |
| 74 | interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; |
| 75 | }; |
| 76 | |
| 77 | soc@9c000000 { |
| 78 | intc: interrupt-controller@780 { |
| 79 | interrupt-parent = <&gic>; |
| 80 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, /* EXT_INT0 */ |
| 81 | <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; /* EXT_INT1 */ |
| 82 | }; |
| 83 | }; |
| 84 | }; |