| Tom Rini | 6b642ac | 2024-10-01 12:20:28 -0600 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/fsi/aspeed,ast2600-fsi-master.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Aspeed FSI master |
| 8 | |
| 9 | maintainers: |
| 10 | - Eddie James <eajames@linux.ibm.com> |
| 11 | |
| 12 | description: |
| 13 | The AST2600 and later contain two identical FSI masters. They share a |
| 14 | clock and have a separate interrupt line and output pins. |
| 15 | |
| 16 | properties: |
| 17 | compatible: |
| 18 | enum: |
| 19 | - aspeed,ast2600-fsi-master |
| 20 | - aspeed,ast2700-fsi-master |
| 21 | |
| 22 | clocks: |
| 23 | maxItems: 1 |
| 24 | |
| 25 | cfam-reset-gpios: |
| 26 | maxItems: 1 |
| 27 | description: |
| 28 | Output GPIO pin for CFAM reset |
| 29 | |
| 30 | fsi-routing-gpios: |
| 31 | maxItems: 1 |
| 32 | description: |
| 33 | Output GPIO pin for setting the FSI mux (internal or cabled) |
| 34 | |
| 35 | fsi-mux-gpios: |
| 36 | maxItems: 1 |
| 37 | description: |
| 38 | Input GPIO pin for detecting the desired FSI mux state |
| 39 | |
| 40 | interrupts: |
| 41 | maxItems: 1 |
| 42 | |
| 43 | if: |
| 44 | properties: |
| 45 | compatible: |
| 46 | contains: |
| 47 | enum: |
| 48 | - aspeed,ast2600-fsi-master |
| 49 | then: |
| 50 | properties: |
| 51 | reg: |
| 52 | maxItems: 1 |
| 53 | else: |
| 54 | properties: |
| 55 | reg: |
| 56 | minItems: 1 |
| 57 | items: |
| 58 | - description: OPB control registers |
| 59 | - description: FSI controller registers |
| 60 | - description: FSI link address space |
| 61 | reg-names: |
| 62 | items: |
| 63 | - const: opb |
| 64 | - const: ctrl |
| 65 | - const: fsi |
| 66 | |
| 67 | required: |
| 68 | - compatible |
| 69 | - reg |
| 70 | - clocks |
| 71 | - interrupts |
| 72 | |
| 73 | allOf: |
| 74 | - $ref: fsi-controller.yaml# |
| 75 | |
| 76 | unevaluatedProperties: false |
| 77 | |
| 78 | examples: |
| 79 | - | |
| 80 | #include <dt-bindings/clock/ast2600-clock.h> |
| 81 | #include <dt-bindings/gpio/aspeed-gpio.h> |
| 82 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 83 | fsi-master@1e79b000 { |
| 84 | compatible = "aspeed,ast2600-fsi-master"; |
| 85 | reg = <0x1e79b000 0x94>; |
| 86 | #address-cells = <2>; |
| 87 | #size-cells = <0>; |
| 88 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; |
| 89 | pinctrl-names = "default"; |
| 90 | pinctrl-0 = <&pinctrl_fsi1_default>; |
| 91 | clocks = <&syscon ASPEED_CLK_GATE_FSICLK>; |
| 92 | fsi-routing-gpios = <&gpio0 ASPEED_GPIO(Q, 7) GPIO_ACTIVE_HIGH>; |
| 93 | fsi-mux-gpios = <&gpio0 ASPEED_GPIO(B, 0) GPIO_ACTIVE_HIGH>; |
| 94 | cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_LOW>; |
| 95 | |
| 96 | cfam@0,0 { |
| 97 | reg = <0 0>; |
| 98 | #address-cells = <1>; |
| 99 | #size-cells = <1>; |
| 100 | chip-id = <0>; |
| 101 | }; |
| 102 | }; |
| 103 | - | |
| 104 | bus { |
| 105 | #address-cells = <2>; |
| 106 | #size-cells = <2>; |
| 107 | |
| 108 | fsi-master@21800000 { |
| 109 | compatible = "aspeed,ast2700-fsi-master"; |
| 110 | reg = <0x0 0x21800000 0x0 0x100>, |
| 111 | <0x0 0x21000000 0x0 0x1000>, |
| 112 | <0x0 0x20000000 0x0 0x1000000>; |
| 113 | reg-names = "opb", "ctrl", "fsi"; |
| 114 | #interrupt-cells = <1>; |
| 115 | interrupt-controller; |
| 116 | interrupts-extended = <&intc 6>; |
| 117 | pinctrl-names = "default"; |
| 118 | pinctrl-0 = <&pinctrl_fsi0_default>; |
| 119 | clocks = <&syscon 40>; |
| 120 | }; |
| 121 | }; |