blob: 63aa5c946696ee0368bb3453b40ff0110f0fbcfd [file] [log] [blame]
Mario Sixf62074e2019-01-21 09:18:13 +01001#define SPCR_PCIHPE_MASK 0x10000000
2#define SPCR_PCIPR_MASK 0x03000000
3#define SPCR_OPT_MASK 0x00800000
4#define SPCR_TBEN_MASK 0x00400000
5#define SPCR_COREPR_MASK 0x00300000
6#define SPCR_TSEC1DP_MASK 0x00003000
7#define SPCR_TSEC1BDP_MASK 0x00000C00
8#define SPCR_TSEC1EP_MASK 0x00000300
9#define SPCR_TSEC2DP_MASK 0x00000030
10#define SPCR_TSEC2BDP_MASK 0x0000000C
11#define SPCR_TSEC2EP_MASK 0x00000003
12#define SPCR_TSECDP_MASK 0x00003000
13#define SPCR_TSECBDP_MASK 0x00000C00
14#define SPCR_TSECEP_MASK 0x00000300
15
16 const __be32 spcr_mask =
17#if defined(CONFIG_SPCR_OPT) && !defined(CONFIG_SPCR_OPT_UNSET)
18 SPCR_OPT_MASK |
19#endif
20#if defined(CONFIG_SPCR_TSECEP) && !defined(CONFIG_SPCR_TSECEP_UNSET)
21 SPCR_TSECEP_MASK |
22#endif
23#if defined(CONFIG_SPCR_TSEC1EP) && !defined(CONFIG_SPCR_TSEC1EP_UNSET)
24 SPCR_TSEC1EP_MASK |
25#endif
26#if defined(CONFIG_SPCR_TSEC2EP) && !defined(CONFIG_SPCR_TSEC2EP_UNSET)
27 SPCR_TSEC2EP_MASK |
28#endif
29 0;
30 const __be32 spcr_val =
31#if defined(CONFIG_SPCR_OPT) && !defined(CONFIG_SPCR_OPT_UNSET)
32 CONFIG_SPCR_OPT |
33#endif
34#if defined(CONFIG_SPCR_TSECEP) && !defined(CONFIG_SPCR_TSECEP_UNSET)
35 CONFIG_SPCR_TSECEP |
36#endif
37#if defined(CONFIG_SPCR_TSEC1EP) && !defined(CONFIG_SPCR_TSEC1EP_UNSET)
38 CONFIG_SPCR_TSEC1EP |
39#endif
40#if defined(CONFIG_SPCR_TSEC2EP) && !defined(CONFIG_SPCR_TSEC2EP_UNSET)
41 CONFIG_SPCR_TSEC2EP |
42#endif
43 0;
Mario Six98d7eaa2019-01-21 09:18:14 +010044
45 const __be32 lcrr_mask =
46#if defined(CONFIG_LCRR_DBYP) && !defined(CONFIG_LCRR_DBYP_UNSET)
47 LCRR_DBYP |
48#endif
49#if defined(CONFIG_LCRR_BUFCMDC) && !defined(CONFIG_LCRR_BUFCMDC_UNSET)
50 LCRR_BUFCMDC |
51#endif
52#if defined(CONFIG_LCRR_ECL) && !defined(CONFIG_LCRR_ECL_UNSET)
53 LCRR_ECL |
54#endif
55#if defined(CONFIG_LCRR_EADC) && !defined(CONFIG_LCRR_EADC_UNSET)
56 LCRR_EADC |
57#endif
58#if defined(CONFIG_LCRR_CLKDIV) && !defined(CONFIG_LCRR_CLKDIV_UNSET)
59 LCRR_CLKDIV |
60#endif
61 0;
62
63 const __be32 lcrr_val =
64#if defined(CONFIG_LCRR_DBYP) && !defined(CONFIG_LCRR_DBYP_UNSET)
65 CONFIG_LCRR_DBYP |
66#endif
67#if defined(CONFIG_LCRR_BUFCMDC) && !defined(CONFIG_LCRR_BUFCMDC_UNSET)
68 CONFIG_LCRR_BUFCMDC |
69#endif
70#if defined(CONFIG_LCRR_ECL) && !defined(CONFIG_LCRR_ECL_UNSET)
71 CONFIG_LCRR_ECL |
72#endif
73#if defined(CONFIG_LCRR_EADC) && !defined(CONFIG_LCRR_EADC_UNSET)
74 CONFIG_LCRR_EADC |
75#endif
76#if defined(CONFIG_LCRR_CLKDIV) && !defined(CONFIG_LCRR_CLKDIV_UNSET)
77 CONFIG_LCRR_CLKDIV |
78#endif
79 0;