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git01.mediatek.com / filogic / uboot / 45140f066a9abe616efe58d3d76123dd75dbe790 / . / drivers / pinctrl / renesas / pfc-r8a7792.c
blob: 81cfe81c7f549ac630b34a91b90781997480c9d4 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2/*
3 * r8a7792 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2013-2014 Renesas Electronics Corporation
6 * Copyright (C) 2016 Cogent Embedded, Inc., <source@cogentembedded.com>
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]7 */
8
9#include <common.h>
10#include <dm.h>
11#include <errno.h>
12#include <dm/pinctrl.h>
13#include <linux/kernel.h>
14
15#include "sh_pfc.h"
16
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]17#define CPU_ALL_GP(fn, sfx) \
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]18 PORT_GP_CFG_29(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
19 PORT_GP_CFG_23(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
20 PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
21 PORT_GP_CFG_28(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
22 PORT_GP_CFG_17(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
23 PORT_GP_CFG_17(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
24 PORT_GP_CFG_17(6, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
25 PORT_GP_CFG_17(7, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
26 PORT_GP_CFG_17(8, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
27 PORT_GP_CFG_17(9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
28 PORT_GP_CFG_32(10, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
29 PORT_GP_CFG_30(11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
30
31#define CPU_ALL_NOGP(fn) \
32 PIN_NOGP_CFG(DU0_DOTCLKIN, "DU0_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_UP), \
33 PIN_NOGP_CFG(DU0_DOTCLKOUT, "DU0_DOTCLKOUT", fn, SH_PFC_PIN_CFG_PULL_UP), \
34 PIN_NOGP_CFG(DU1_DOTCLKIN, "DU1_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_UP), \
35 PIN_NOGP_CFG(DU1_DOTCLKOUT, "DU1_DOTCLKOUT", fn, SH_PFC_PIN_CFG_PULL_UP), \
36 PIN_NOGP_CFG(EDBGREQ, "EDBGREQ", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
37 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
38 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
39 PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
40 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]41
42enum {
43 PINMUX_RESERVED = 0,
44
45 PINMUX_DATA_BEGIN,
46 GP_ALL(DATA),
47 PINMUX_DATA_END,
48
49 PINMUX_FUNCTION_BEGIN,
50 GP_ALL(FN),
51
52 /* GPSR0 */
53 FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
54 FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
55 FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_16,
56 FN_IP0_17, FN_IP0_18, FN_IP0_19, FN_IP0_20, FN_IP0_21,
57 FN_IP0_22, FN_IP0_23, FN_IP1_0, FN_IP1_1, FN_IP1_2,
58 FN_IP1_3, FN_IP1_4,
59
60 /* GPSR1 */
61 FN_IP1_5, FN_IP1_6, FN_IP1_7, FN_IP1_8, FN_IP1_9, FN_IP1_10,
62 FN_IP1_11, FN_IP1_12, FN_IP1_13, FN_IP1_14, FN_IP1_15, FN_IP1_16,
63 FN_DU1_DB2_C0_DATA12, FN_DU1_DB3_C1_DATA13, FN_DU1_DB4_C2_DATA14,
64 FN_DU1_DB5_C3_DATA15, FN_DU1_DB6_C4, FN_DU1_DB7_C5,
65 FN_DU1_EXHSYNC_DU1_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC,
66 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_DU1_DISP, FN_DU1_CDE,
67
68 /* GPSR2 */
69 FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7,
70 FN_D8, FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
71 FN_A0, FN_A1, FN_A2, FN_A3, FN_A4, FN_A5, FN_A6, FN_A7,
72 FN_A8, FN_A9, FN_A10, FN_A11, FN_A12, FN_A13, FN_A14, FN_A15,
73
74 /* GPSR3 */
75 FN_A16, FN_A17, FN_A18, FN_A19, FN_IP1_17, FN_IP1_18,
76 FN_CS1_N_A26, FN_EX_CS0_N, FN_EX_CS1_N, FN_EX_CS2_N, FN_EX_CS3_N,
77 FN_EX_CS4_N, FN_EX_CS5_N, FN_BS_N, FN_RD_N, FN_RD_WR_N,
78 FN_WE0_N, FN_WE1_N, FN_EX_WAIT0, FN_IRQ0, FN_IRQ1, FN_IRQ2, FN_IRQ3,
79 FN_IP1_19, FN_IP1_20, FN_IP1_21, FN_IP1_22, FN_CS0_N,
80
81 /* GPSR4 */
82 FN_VI0_CLK, FN_VI0_CLKENB, FN_VI0_HSYNC_N, FN_VI0_VSYNC_N,
83 FN_VI0_D0_B0_C0, FN_VI0_D1_B1_C1, FN_VI0_D2_B2_C2, FN_VI0_D3_B3_C3,
84 FN_VI0_D4_B4_C4, FN_VI0_D5_B5_C5, FN_VI0_D6_B6_C6, FN_VI0_D7_B7_C7,
85 FN_VI0_D8_G0_Y0, FN_VI0_D9_G1_Y1, FN_VI0_D10_G2_Y2, FN_VI0_D11_G3_Y3,
86 FN_VI0_FIELD,
87
88 /* GPSR5 */
89 FN_VI1_CLK, FN_VI1_CLKENB, FN_VI1_HSYNC_N, FN_VI1_VSYNC_N,
90 FN_VI1_D0_B0_C0, FN_VI1_D1_B1_C1, FN_VI1_D2_B2_C2, FN_VI1_D3_B3_C3,
91 FN_VI1_D4_B4_C4, FN_VI1_D5_B5_C5, FN_VI1_D6_B6_C6, FN_VI1_D7_B7_C7,
92 FN_VI1_D8_G0_Y0, FN_VI1_D9_G1_Y1, FN_VI1_D10_G2_Y2, FN_VI1_D11_G3_Y3,
93 FN_VI1_FIELD,
94
95 /* GPSR6 */
96 FN_IP2_0, FN_IP2_1, FN_IP2_2, FN_IP2_3, FN_IP2_4, FN_IP2_5, FN_IP2_6,
97 FN_IP2_7, FN_IP2_8, FN_IP2_9, FN_IP2_10, FN_IP2_11, FN_IP2_12,
98 FN_IP2_13, FN_IP2_14, FN_IP2_15, FN_IP2_16,
99
100 /* GPSR7 */
101 FN_IP3_0, FN_IP3_1, FN_IP3_2, FN_IP3_3, FN_IP3_4, FN_IP3_5, FN_IP3_6,
102 FN_IP3_7, FN_IP3_8, FN_IP3_9, FN_IP3_10, FN_IP3_11, FN_IP3_12,
103 FN_IP3_13, FN_VI3_D10_Y2, FN_IP3_14, FN_VI3_FIELD,
104
105 /* GPSR8 */
106 FN_VI4_CLK, FN_IP4_0, FN_IP4_1, FN_IP4_3_2, FN_IP4_4, FN_IP4_6_5,
107 FN_IP4_8_7, FN_IP4_10_9, FN_IP4_12_11, FN_IP4_14_13, FN_IP4_16_15,
108 FN_IP4_18_17, FN_IP4_20_19, FN_IP4_21, FN_IP4_22, FN_IP4_23, FN_IP4_24,
109
110 /* GPSR9 */
111 FN_VI5_CLK, FN_IP5_0, FN_IP5_1, FN_IP5_2, FN_IP5_3, FN_IP5_4, FN_IP5_5,
112 FN_IP5_6, FN_IP5_7, FN_IP5_8, FN_IP5_9, FN_IP5_10, FN_IP5_11,
113 FN_VI5_D9_Y1, FN_VI5_D10_Y2, FN_VI5_D11_Y3, FN_VI5_FIELD,
114
115 /* GPSR10 */
116 FN_IP6_0, FN_IP6_1, FN_HRTS0_N, FN_IP6_2, FN_IP6_3, FN_IP6_4, FN_IP6_5,
117 FN_HCTS1_N, FN_IP6_6, FN_IP6_7, FN_SCK0, FN_CTS0_N, FN_RTS0_N,
118 FN_TX0, FN_RX0, FN_SCK1, FN_CTS1_N, FN_RTS1_N, FN_TX1, FN_RX1,
119 FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, FN_IP6_16,
120 FN_IP6_18_17, FN_SCIF_CLK, FN_CAN0_TX, FN_CAN0_RX, FN_CAN_CLK,
121 FN_CAN1_TX, FN_CAN1_RX,
122
123 /* GPSR11 */
124 FN_IP7_1_0, FN_IP7_3_2, FN_IP7_5_4, FN_IP7_6, FN_IP7_7, FN_SD0_CLK,
125 FN_SD0_CMD, FN_SD0_DAT0, FN_SD0_DAT1, FN_SD0_DAT2, FN_SD0_DAT3,
126 FN_SD0_CD, FN_SD0_WP, FN_IP7_9_8, FN_IP7_11_10, FN_IP7_13_12,
127 FN_IP7_15_14, FN_IP7_16, FN_IP7_17, FN_IP7_18, FN_IP7_19, FN_IP7_20,
128 FN_ADICLK, FN_ADICS_SAMP, FN_ADIDATA, FN_ADICHS0, FN_ADICHS1,
129 FN_ADICHS2, FN_AVS1, FN_AVS2,
130
131 /* IPSR0 */
132 FN_DU0_DR0_DATA0, FN_DU0_DR1_DATA1, FN_DU0_DR2_Y4_DATA2,
133 FN_DU0_DR3_Y5_DATA3, FN_DU0_DR4_Y6_DATA4, FN_DU0_DR5_Y7_DATA5,
134 FN_DU0_DR6_Y8_DATA6, FN_DU0_DR7_Y9_DATA7, FN_DU0_DG0_DATA8,
135 FN_DU0_DG1_DATA9, FN_DU0_DG2_C6_DATA10, FN_DU0_DG3_C7_DATA11,
136 FN_DU0_DG4_Y0_DATA12, FN_DU0_DG5_Y1_DATA13, FN_DU0_DG6_Y2_DATA14,
137 FN_DU0_DG7_Y3_DATA15, FN_DU0_DB0, FN_DU0_DB1, FN_DU0_DB2_C0,
138 FN_DU0_DB3_C1, FN_DU0_DB4_C2, FN_DU0_DB5_C3, FN_DU0_DB6_C4,
139 FN_DU0_DB7_C5,
140
141 /* IPSR1 */
142 FN_DU0_EXHSYNC_DU0_HSYNC, FN_DU0_EXVSYNC_DU0_VSYNC,
143 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_DU0_DISP, FN_DU0_CDE,
144 FN_DU1_DR2_Y4_DATA0, FN_DU1_DR3_Y5_DATA1, FN_DU1_DR4_Y6_DATA2,
145 FN_DU1_DR5_Y7_DATA3, FN_DU1_DR6_DATA4, FN_DU1_DR7_DATA5,
146 FN_DU1_DG2_C6_DATA6, FN_DU1_DG3_C7_DATA7, FN_DU1_DG4_Y0_DATA8,
147 FN_DU1_DG5_Y1_DATA9, FN_DU1_DG6_Y2_DATA10, FN_DU1_DG7_Y3_DATA11,
148 FN_A20, FN_MOSI_IO0, FN_A21, FN_MISO_IO1, FN_A22, FN_IO2,
149 FN_A23, FN_IO3, FN_A24, FN_SPCLK, FN_A25, FN_SSL,
150
151 /* IPSR2 */
152 FN_VI2_CLK, FN_AVB_RX_CLK, FN_VI2_CLKENB, FN_AVB_RX_DV,
153 FN_VI2_HSYNC_N, FN_AVB_RXD0, FN_VI2_VSYNC_N, FN_AVB_RXD1,
154 FN_VI2_D0_C0, FN_AVB_RXD2, FN_VI2_D1_C1, FN_AVB_RXD3,
155 FN_VI2_D2_C2, FN_AVB_RXD4, FN_VI2_D3_C3, FN_AVB_RXD5,
156 FN_VI2_D4_C4, FN_AVB_RXD6, FN_VI2_D5_C5, FN_AVB_RXD7,
157 FN_VI2_D6_C6, FN_AVB_RX_ER, FN_VI2_D7_C7, FN_AVB_COL,
158 FN_VI2_D8_Y0, FN_AVB_TXD3, FN_VI2_D9_Y1, FN_AVB_TX_EN,
159 FN_VI2_D10_Y2, FN_AVB_TXD0, FN_VI2_D11_Y3, FN_AVB_TXD1,
160 FN_VI2_FIELD, FN_AVB_TXD2,
161
162 /* IPSR3 */
163 FN_VI3_CLK, FN_AVB_TX_CLK, FN_VI3_CLKENB, FN_AVB_TXD4,
164 FN_VI3_HSYNC_N, FN_AVB_TXD5, FN_VI3_VSYNC_N, FN_AVB_TXD6,
165 FN_VI3_D0_C0, FN_AVB_TXD7, FN_VI3_D1_C1, FN_AVB_TX_ER,
166 FN_VI3_D2_C2, FN_AVB_GTX_CLK, FN_VI3_D3_C3, FN_AVB_MDC,
167 FN_VI3_D4_C4, FN_AVB_MDIO, FN_VI3_D5_C5, FN_AVB_LINK,
168 FN_VI3_D6_C6, FN_AVB_MAGIC, FN_VI3_D7_C7, FN_AVB_PHY_INT,
169 FN_VI3_D8_Y0, FN_AVB_CRS, FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,
170 FN_VI3_D11_Y3, FN_AVB_AVTP_MATCH,
171
172 /* IPSR4 */
173 FN_VI4_CLKENB, FN_VI0_D12_G4_Y4, FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5,
174 FN_VI4_VSYNC_N, FN_VI0_D14_G6_Y6, FN_RDR_CLKOUT,
175 FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,
176 FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4,
177 FN_VI4_D2_C2, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5,
178 FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6,
179 FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7,
180 FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4,
181 FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5,
182 FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6,
183 FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7,
184 FN_VI4_D9_Y1, FN_VI3_D12_Y4, FN_VI4_D10_Y2, FN_VI3_D13_Y5,
185 FN_VI4_D11_Y3, FN_VI3_D14_Y6, FN_VI4_FIELD, FN_VI3_D15_Y7,
186
187 /* IPSR5 */
188 FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B, FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B,
189 FN_VI5_VSYNC_N, FN_VI1_D14_G6_Y6_B, FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_B,
190 FN_VI5_D1_C1, FN_VI1_D16_R0, FN_VI5_D2_C2, FN_VI1_D17_R1,
191 FN_VI5_D3_C3, FN_VI1_D18_R2, FN_VI5_D4_C4, FN_VI1_D19_R3,
192 FN_VI5_D5_C5, FN_VI1_D20_R4, FN_VI5_D6_C6, FN_VI1_D21_R5,
193 FN_VI5_D7_C7, FN_VI1_D22_R6, FN_VI5_D8_Y0, FN_VI1_D23_R7,
194
195 /* IPSR6 */
196 FN_MSIOF0_SCK, FN_HSCK0, FN_MSIOF0_SYNC, FN_HCTS0_N,
197 FN_MSIOF0_TXD, FN_HTX0, FN_MSIOF0_RXD, FN_HRX0,
198 FN_MSIOF1_SCK, FN_HSCK1, FN_MSIOF1_SYNC, FN_HRTS1_N,
199 FN_MSIOF1_TXD, FN_HTX1, FN_MSIOF1_RXD, FN_HRX1,
200 FN_DRACK0, FN_SCK2, FN_DACK0, FN_TX2, FN_DREQ0_N, FN_RX2,
201 FN_DACK1, FN_SCK3, FN_TX3, FN_DREQ1_N, FN_RX3,
202
203 /* IPSR7 */
204 FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, FN_PWM1, FN_TCLK2, FN_FSO_CFE_1,
205 FN_PWM2, FN_TCLK3, FN_FSO_TOE, FN_PWM3, FN_PWM4,
206 FN_SSI_SCK34, FN_TPU0TO0, FN_SSI_WS34, FN_TPU0TO1,
207 FN_SSI_SDATA3, FN_TPU0TO2, FN_SSI_SCK4, FN_TPU0TO3,
208 FN_SSI_WS4, FN_SSI_SDATA4, FN_AUDIO_CLKOUT,
209 FN_AUDIO_CLKA, FN_AUDIO_CLKB,
210
211 /* MOD_SEL */
212 FN_SEL_VI1_0, FN_SEL_VI1_1,
213 PINMUX_FUNCTION_END,
214
215 PINMUX_MARK_BEGIN,
216 DU1_DB2_C0_DATA12_MARK, DU1_DB3_C1_DATA13_MARK,
217 DU1_DB4_C2_DATA14_MARK, DU1_DB5_C3_DATA15_MARK,
218 DU1_DB6_C4_MARK, DU1_DB7_C5_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
219 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
220 DU1_DISP_MARK, DU1_CDE_MARK,
221
222 D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK, D6_MARK,
223 D7_MARK, D8_MARK, D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK,
224 D14_MARK, D15_MARK, A0_MARK, A1_MARK, A2_MARK, A3_MARK, A4_MARK,
225 A5_MARK, A6_MARK, A7_MARK, A8_MARK, A9_MARK, A10_MARK, A11_MARK,
226 A12_MARK, A13_MARK, A14_MARK, A15_MARK,
227
228 A16_MARK, A17_MARK, A18_MARK, A19_MARK, CS1_N_A26_MARK,
229 EX_CS0_N_MARK, EX_CS1_N_MARK, EX_CS2_N_MARK, EX_CS3_N_MARK,
230 EX_CS4_N_MARK, EX_CS5_N_MARK, BS_N_MARK, RD_N_MARK, RD_WR_N_MARK,
231 WE0_N_MARK, WE1_N_MARK, EX_WAIT0_MARK,
232 IRQ0_MARK, IRQ1_MARK, IRQ2_MARK, IRQ3_MARK, CS0_N_MARK,
233
234 VI0_CLK_MARK, VI0_CLKENB_MARK, VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
235 VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK, VI0_D2_B2_C2_MARK,
236 VI0_D3_B3_C3_MARK, VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
237 VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK, VI0_D8_G0_Y0_MARK,
238 VI0_D9_G1_Y1_MARK, VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
239 VI0_FIELD_MARK,
240
241 VI1_CLK_MARK, VI1_CLKENB_MARK, VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
242 VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK, VI1_D2_B2_C2_MARK,
243 VI1_D3_B3_C3_MARK, VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
244 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK, VI1_D8_G0_Y0_MARK,
245 VI1_D9_G1_Y1_MARK, VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
246 VI1_FIELD_MARK,
247
248 VI3_D10_Y2_MARK, VI3_FIELD_MARK,
249
250 VI4_CLK_MARK,
251
252 VI5_CLK_MARK, VI5_D9_Y1_MARK, VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,
253 VI5_FIELD_MARK,
254
255 HRTS0_N_MARK, HCTS1_N_MARK, SCK0_MARK, CTS0_N_MARK, RTS0_N_MARK,
256 TX0_MARK, RX0_MARK, SCK1_MARK, CTS1_N_MARK, RTS1_N_MARK,
257 TX1_MARK, RX1_MARK, SCIF_CLK_MARK, CAN0_TX_MARK, CAN0_RX_MARK,
258 CAN_CLK_MARK, CAN1_TX_MARK, CAN1_RX_MARK,
259
260 SD0_CLK_MARK, SD0_CMD_MARK, SD0_DAT0_MARK, SD0_DAT1_MARK,
261 SD0_DAT2_MARK, SD0_DAT3_MARK, SD0_CD_MARK, SD0_WP_MARK,
262 ADICLK_MARK, ADICS_SAMP_MARK, ADIDATA_MARK, ADICHS0_MARK,
263 ADICHS1_MARK, ADICHS2_MARK, AVS1_MARK, AVS2_MARK,
264
265 /* IPSR0 */
266 DU0_DR0_DATA0_MARK, DU0_DR1_DATA1_MARK, DU0_DR2_Y4_DATA2_MARK,
267 DU0_DR3_Y5_DATA3_MARK, DU0_DR4_Y6_DATA4_MARK, DU0_DR5_Y7_DATA5_MARK,
268 DU0_DR6_Y8_DATA6_MARK, DU0_DR7_Y9_DATA7_MARK, DU0_DG0_DATA8_MARK,
269 DU0_DG1_DATA9_MARK, DU0_DG2_C6_DATA10_MARK, DU0_DG3_C7_DATA11_MARK,
270 DU0_DG4_Y0_DATA12_MARK, DU0_DG5_Y1_DATA13_MARK, DU0_DG6_Y2_DATA14_MARK,
271 DU0_DG7_Y3_DATA15_MARK, DU0_DB0_MARK, DU0_DB1_MARK,
272 DU0_DB2_C0_MARK, DU0_DB3_C1_MARK, DU0_DB4_C2_MARK, DU0_DB5_C3_MARK,
273 DU0_DB6_C4_MARK, DU0_DB7_C5_MARK,
274
275 /* IPSR1 */
276 DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
277 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, DU0_DISP_MARK, DU0_CDE_MARK,
278 DU1_DR2_Y4_DATA0_MARK, DU1_DR3_Y5_DATA1_MARK, DU1_DR4_Y6_DATA2_MARK,
279 DU1_DR5_Y7_DATA3_MARK, DU1_DR6_DATA4_MARK, DU1_DR7_DATA5_MARK,
280 DU1_DG2_C6_DATA6_MARK, DU1_DG3_C7_DATA7_MARK, DU1_DG4_Y0_DATA8_MARK,
281 DU1_DG5_Y1_DATA9_MARK, DU1_DG6_Y2_DATA10_MARK, DU1_DG7_Y3_DATA11_MARK,
282 A20_MARK, MOSI_IO0_MARK, A21_MARK, MISO_IO1_MARK, A22_MARK, IO2_MARK,
283 A23_MARK, IO3_MARK, A24_MARK, SPCLK_MARK, A25_MARK, SSL_MARK,
284
285 /* IPSR2 */
286 VI2_CLK_MARK, AVB_RX_CLK_MARK, VI2_CLKENB_MARK, AVB_RX_DV_MARK,
287 VI2_HSYNC_N_MARK, AVB_RXD0_MARK, VI2_VSYNC_N_MARK, AVB_RXD1_MARK,
288 VI2_D0_C0_MARK, AVB_RXD2_MARK, VI2_D1_C1_MARK, AVB_TX_CLK_MARK,
289 VI2_D2_C2_MARK, AVB_RXD4_MARK, VI2_D3_C3_MARK, AVB_RXD5_MARK,
290 VI2_D4_C4_MARK, AVB_RXD6_MARK, VI2_D5_C5_MARK, AVB_RXD7_MARK,
291 VI2_D6_C6_MARK, AVB_RX_ER_MARK, VI2_D7_C7_MARK, AVB_COL_MARK,
292 VI2_D8_Y0_MARK, AVB_RXD3_MARK, VI2_D9_Y1_MARK, AVB_TX_EN_MARK,
293 VI2_D10_Y2_MARK, AVB_TXD0_MARK,
294 VI2_D11_Y3_MARK, AVB_TXD1_MARK, VI2_FIELD_MARK, AVB_TXD2_MARK,
295
296 /* IPSR3 */
297 VI3_CLK_MARK, AVB_TXD3_MARK, VI3_CLKENB_MARK, AVB_TXD4_MARK,
298 VI3_HSYNC_N_MARK, AVB_TXD5_MARK, VI3_VSYNC_N_MARK, AVB_TXD6_MARK,
299 VI3_D0_C0_MARK, AVB_TXD7_MARK, VI3_D1_C1_MARK, AVB_TX_ER_MARK,
300 VI3_D2_C2_MARK, AVB_GTX_CLK_MARK, VI3_D3_C3_MARK, AVB_MDC_MARK,
301 VI3_D4_C4_MARK, AVB_MDIO_MARK, VI3_D5_C5_MARK, AVB_LINK_MARK,
302 VI3_D6_C6_MARK, AVB_MAGIC_MARK, VI3_D7_C7_MARK, AVB_PHY_INT_MARK,
303 VI3_D8_Y0_MARK, AVB_CRS_MARK, VI3_D9_Y1_MARK, AVB_GTXREFCLK_MARK,
304 VI3_D11_Y3_MARK, AVB_AVTP_MATCH_MARK,
305
306 /* IPSR4 */
307 VI4_CLKENB_MARK, VI0_D12_G4_Y4_MARK, VI4_HSYNC_N_MARK,
308 VI0_D13_G5_Y5_MARK, VI4_VSYNC_N_MARK, VI0_D14_G6_Y6_MARK,
309 RDR_CLKOUT_MARK, VI4_D0_C0_MARK, VI0_D15_G7_Y7_MARK, VI4_D1_C1_MARK,
310 VI0_D16_R0_MARK, VI1_D12_G4_Y4_MARK, VI4_D2_C2_MARK, VI0_D17_R1_MARK,
311 VI1_D13_G5_Y5_MARK, VI4_D3_C3_MARK, VI0_D18_R2_MARK, VI1_D14_G6_Y6_MARK,
312 VI4_D4_C4_MARK, VI0_D19_R3_MARK, VI1_D15_G7_Y7_MARK, VI4_D5_C5_MARK,
313 VI0_D20_R4_MARK, VI2_D12_Y4_MARK, VI4_D6_C6_MARK, VI0_D21_R5_MARK,
314 VI2_D13_Y5_MARK, VI4_D7_C7_MARK, VI0_D22_R6_MARK, VI2_D14_Y6_MARK,
315 VI4_D8_Y0_MARK, VI0_D23_R7_MARK, VI2_D15_Y7_MARK, VI4_D9_Y1_MARK,
316 VI3_D12_Y4_MARK, VI4_D10_Y2_MARK, VI3_D13_Y5_MARK, VI4_D11_Y3_MARK,
317 VI3_D14_Y6_MARK, VI4_FIELD_MARK, VI3_D15_Y7_MARK,
318
319 /* IPSR5 */
320 VI5_CLKENB_MARK, VI1_D12_G4_Y4_B_MARK, VI5_HSYNC_N_MARK,
321 VI1_D13_G5_Y5_B_MARK, VI5_VSYNC_N_MARK, VI1_D14_G6_Y6_B_MARK,
322 VI5_D0_C0_MARK, VI1_D15_G7_Y7_B_MARK, VI5_D1_C1_MARK, VI1_D16_R0_MARK,
323 VI5_D2_C2_MARK, VI1_D17_R1_MARK, VI5_D3_C3_MARK, VI1_D18_R2_MARK,
324 VI5_D4_C4_MARK, VI1_D19_R3_MARK, VI5_D5_C5_MARK, VI1_D20_R4_MARK,
325 VI5_D6_C6_MARK, VI1_D21_R5_MARK, VI5_D7_C7_MARK, VI1_D22_R6_MARK,
326 VI5_D8_Y0_MARK, VI1_D23_R7_MARK,
327
328 /* IPSR6 */
329 MSIOF0_SCK_MARK, HSCK0_MARK, MSIOF0_SYNC_MARK, HCTS0_N_MARK,
330 MSIOF0_TXD_MARK, HTX0_MARK, MSIOF0_RXD_MARK, HRX0_MARK,
331 MSIOF1_SCK_MARK, HSCK1_MARK, MSIOF1_SYNC_MARK, HRTS1_N_MARK,
332 MSIOF1_TXD_MARK, HTX1_MARK, MSIOF1_RXD_MARK, HRX1_MARK,
333 DRACK0_MARK, SCK2_MARK, DACK0_MARK, TX2_MARK, DREQ0_N_MARK,
334 RX2_MARK, DACK1_MARK, SCK3_MARK, TX3_MARK, DREQ1_N_MARK,
335 RX3_MARK,
336
337 /* IPSR7 */
338 PWM0_MARK, TCLK1_MARK, FSO_CFE_0_MARK, PWM1_MARK, TCLK2_MARK,
339 FSO_CFE_1_MARK, PWM2_MARK, TCLK3_MARK, FSO_TOE_MARK, PWM3_MARK,
340 PWM4_MARK, SSI_SCK34_MARK, TPU0TO0_MARK, SSI_WS34_MARK, TPU0TO1_MARK,
341 SSI_SDATA3_MARK, TPU0TO2_MARK, SSI_SCK4_MARK, TPU0TO3_MARK,
342 SSI_WS4_MARK, SSI_SDATA4_MARK, AUDIO_CLKOUT_MARK, AUDIO_CLKA_MARK,
343 AUDIO_CLKB_MARK,
344 PINMUX_MARK_END,
345};
346
347static const u16 pinmux_data[] = {
348 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
349
350 PINMUX_SINGLE(DU1_DB2_C0_DATA12),
351 PINMUX_SINGLE(DU1_DB3_C1_DATA13),
352 PINMUX_SINGLE(DU1_DB4_C2_DATA14),
353 PINMUX_SINGLE(DU1_DB5_C3_DATA15),
354 PINMUX_SINGLE(DU1_DB6_C4),
355 PINMUX_SINGLE(DU1_DB7_C5),
356 PINMUX_SINGLE(DU1_EXHSYNC_DU1_HSYNC),
357 PINMUX_SINGLE(DU1_EXVSYNC_DU1_VSYNC),
358 PINMUX_SINGLE(DU1_EXODDF_DU1_ODDF_DISP_CDE),
359 PINMUX_SINGLE(DU1_DISP),
360 PINMUX_SINGLE(DU1_CDE),
361 PINMUX_SINGLE(D0),
362 PINMUX_SINGLE(D1),
363 PINMUX_SINGLE(D2),
364 PINMUX_SINGLE(D3),
365 PINMUX_SINGLE(D4),
366 PINMUX_SINGLE(D5),
367 PINMUX_SINGLE(D6),
368 PINMUX_SINGLE(D7),
369 PINMUX_SINGLE(D8),
370 PINMUX_SINGLE(D9),
371 PINMUX_SINGLE(D10),
372 PINMUX_SINGLE(D11),
373 PINMUX_SINGLE(D12),
374 PINMUX_SINGLE(D13),
375 PINMUX_SINGLE(D14),
376 PINMUX_SINGLE(D15),
377 PINMUX_SINGLE(A0),
378 PINMUX_SINGLE(A1),
379 PINMUX_SINGLE(A2),
380 PINMUX_SINGLE(A3),
381 PINMUX_SINGLE(A4),
382 PINMUX_SINGLE(A5),
383 PINMUX_SINGLE(A6),
384 PINMUX_SINGLE(A7),
385 PINMUX_SINGLE(A8),
386 PINMUX_SINGLE(A9),
387 PINMUX_SINGLE(A10),
388 PINMUX_SINGLE(A11),
389 PINMUX_SINGLE(A12),
390 PINMUX_SINGLE(A13),
391 PINMUX_SINGLE(A14),
392 PINMUX_SINGLE(A15),
393 PINMUX_SINGLE(A16),
394 PINMUX_SINGLE(A17),
395 PINMUX_SINGLE(A18),
396 PINMUX_SINGLE(A19),
397 PINMUX_SINGLE(CS1_N_A26),
398 PINMUX_SINGLE(EX_CS0_N),
399 PINMUX_SINGLE(EX_CS1_N),
400 PINMUX_SINGLE(EX_CS2_N),
401 PINMUX_SINGLE(EX_CS3_N),
402 PINMUX_SINGLE(EX_CS4_N),
403 PINMUX_SINGLE(EX_CS5_N),
404 PINMUX_SINGLE(BS_N),
405 PINMUX_SINGLE(RD_N),
406 PINMUX_SINGLE(RD_WR_N),
407 PINMUX_SINGLE(WE0_N),
408 PINMUX_SINGLE(WE1_N),
409 PINMUX_SINGLE(EX_WAIT0),
410 PINMUX_SINGLE(IRQ0),
411 PINMUX_SINGLE(IRQ1),
412 PINMUX_SINGLE(IRQ2),
413 PINMUX_SINGLE(IRQ3),
414 PINMUX_SINGLE(CS0_N),
415 PINMUX_SINGLE(VI0_CLK),
416 PINMUX_SINGLE(VI0_CLKENB),
417 PINMUX_SINGLE(VI0_HSYNC_N),
418 PINMUX_SINGLE(VI0_VSYNC_N),
419 PINMUX_SINGLE(VI0_D0_B0_C0),
420 PINMUX_SINGLE(VI0_D1_B1_C1),
421 PINMUX_SINGLE(VI0_D2_B2_C2),
422 PINMUX_SINGLE(VI0_D3_B3_C3),
423 PINMUX_SINGLE(VI0_D4_B4_C4),
424 PINMUX_SINGLE(VI0_D5_B5_C5),
425 PINMUX_SINGLE(VI0_D6_B6_C6),
426 PINMUX_SINGLE(VI0_D7_B7_C7),
427 PINMUX_SINGLE(VI0_D8_G0_Y0),
428 PINMUX_SINGLE(VI0_D9_G1_Y1),
429 PINMUX_SINGLE(VI0_D10_G2_Y2),
430 PINMUX_SINGLE(VI0_D11_G3_Y3),
431 PINMUX_SINGLE(VI0_FIELD),
432 PINMUX_SINGLE(VI1_CLK),
433 PINMUX_SINGLE(VI1_CLKENB),
434 PINMUX_SINGLE(VI1_HSYNC_N),
435 PINMUX_SINGLE(VI1_VSYNC_N),
436 PINMUX_SINGLE(VI1_D0_B0_C0),
437 PINMUX_SINGLE(VI1_D1_B1_C1),
438 PINMUX_SINGLE(VI1_D2_B2_C2),
439 PINMUX_SINGLE(VI1_D3_B3_C3),
440 PINMUX_SINGLE(VI1_D4_B4_C4),
441 PINMUX_SINGLE(VI1_D5_B5_C5),
442 PINMUX_SINGLE(VI1_D6_B6_C6),
443 PINMUX_SINGLE(VI1_D7_B7_C7),
444 PINMUX_SINGLE(VI1_D8_G0_Y0),
445 PINMUX_SINGLE(VI1_D9_G1_Y1),
446 PINMUX_SINGLE(VI1_D10_G2_Y2),
447 PINMUX_SINGLE(VI1_D11_G3_Y3),
448 PINMUX_SINGLE(VI1_FIELD),
449 PINMUX_SINGLE(VI3_D10_Y2),
450 PINMUX_SINGLE(VI3_FIELD),
451 PINMUX_SINGLE(VI4_CLK),
452 PINMUX_SINGLE(VI5_CLK),
453 PINMUX_SINGLE(VI5_D9_Y1),
454 PINMUX_SINGLE(VI5_D10_Y2),
455 PINMUX_SINGLE(VI5_D11_Y3),
456 PINMUX_SINGLE(VI5_FIELD),
457 PINMUX_SINGLE(HRTS0_N),
458 PINMUX_SINGLE(HCTS1_N),
459 PINMUX_SINGLE(SCK0),
460 PINMUX_SINGLE(CTS0_N),
461 PINMUX_SINGLE(RTS0_N),
462 PINMUX_SINGLE(TX0),
463 PINMUX_SINGLE(RX0),
464 PINMUX_SINGLE(SCK1),
465 PINMUX_SINGLE(CTS1_N),
466 PINMUX_SINGLE(RTS1_N),
467 PINMUX_SINGLE(TX1),
468 PINMUX_SINGLE(RX1),
469 PINMUX_SINGLE(SCIF_CLK),
470 PINMUX_SINGLE(CAN0_TX),
471 PINMUX_SINGLE(CAN0_RX),
472 PINMUX_SINGLE(CAN_CLK),
473 PINMUX_SINGLE(CAN1_TX),
474 PINMUX_SINGLE(CAN1_RX),
475 PINMUX_SINGLE(SD0_CLK),
476 PINMUX_SINGLE(SD0_CMD),
477 PINMUX_SINGLE(SD0_DAT0),
478 PINMUX_SINGLE(SD0_DAT1),
479 PINMUX_SINGLE(SD0_DAT2),
480 PINMUX_SINGLE(SD0_DAT3),
481 PINMUX_SINGLE(SD0_CD),
482 PINMUX_SINGLE(SD0_WP),
483 PINMUX_SINGLE(ADICLK),
484 PINMUX_SINGLE(ADICS_SAMP),
485 PINMUX_SINGLE(ADIDATA),
486 PINMUX_SINGLE(ADICHS0),
487 PINMUX_SINGLE(ADICHS1),
488 PINMUX_SINGLE(ADICHS2),
489 PINMUX_SINGLE(AVS1),
490 PINMUX_SINGLE(AVS2),
491
492 /* IPSR0 */
493 PINMUX_IPSR_GPSR(IP0_0, DU0_DR0_DATA0),
494 PINMUX_IPSR_GPSR(IP0_1, DU0_DR1_DATA1),
495 PINMUX_IPSR_GPSR(IP0_2, DU0_DR2_Y4_DATA2),
496 PINMUX_IPSR_GPSR(IP0_3, DU0_DR3_Y5_DATA3),
497 PINMUX_IPSR_GPSR(IP0_4, DU0_DR4_Y6_DATA4),
498 PINMUX_IPSR_GPSR(IP0_5, DU0_DR5_Y7_DATA5),
499 PINMUX_IPSR_GPSR(IP0_6, DU0_DR6_Y8_DATA6),
500 PINMUX_IPSR_GPSR(IP0_7, DU0_DR7_Y9_DATA7),
501 PINMUX_IPSR_GPSR(IP0_8, DU0_DG0_DATA8),
502 PINMUX_IPSR_GPSR(IP0_9, DU0_DG1_DATA9),
503 PINMUX_IPSR_GPSR(IP0_10, DU0_DG2_C6_DATA10),
504 PINMUX_IPSR_GPSR(IP0_11, DU0_DG3_C7_DATA11),
505 PINMUX_IPSR_GPSR(IP0_12, DU0_DG4_Y0_DATA12),
506 PINMUX_IPSR_GPSR(IP0_13, DU0_DG5_Y1_DATA13),
507 PINMUX_IPSR_GPSR(IP0_14, DU0_DG6_Y2_DATA14),
508 PINMUX_IPSR_GPSR(IP0_15, DU0_DG7_Y3_DATA15),
509 PINMUX_IPSR_GPSR(IP0_16, DU0_DB0),
510 PINMUX_IPSR_GPSR(IP0_17, DU0_DB1),
511 PINMUX_IPSR_GPSR(IP0_18, DU0_DB2_C0),
512 PINMUX_IPSR_GPSR(IP0_19, DU0_DB3_C1),
513 PINMUX_IPSR_GPSR(IP0_20, DU0_DB4_C2),
514 PINMUX_IPSR_GPSR(IP0_21, DU0_DB5_C3),
515 PINMUX_IPSR_GPSR(IP0_22, DU0_DB6_C4),
516 PINMUX_IPSR_GPSR(IP0_23, DU0_DB7_C5),
517
518 /* IPSR1 */
519 PINMUX_IPSR_GPSR(IP1_0, DU0_EXHSYNC_DU0_HSYNC),
520 PINMUX_IPSR_GPSR(IP1_1, DU0_EXVSYNC_DU0_VSYNC),
521 PINMUX_IPSR_GPSR(IP1_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
522 PINMUX_IPSR_GPSR(IP1_3, DU0_DISP),
523 PINMUX_IPSR_GPSR(IP1_4, DU0_CDE),
524 PINMUX_IPSR_GPSR(IP1_5, DU1_DR2_Y4_DATA0),
525 PINMUX_IPSR_GPSR(IP1_6, DU1_DR3_Y5_DATA1),
526 PINMUX_IPSR_GPSR(IP1_7, DU1_DR4_Y6_DATA2),
527 PINMUX_IPSR_GPSR(IP1_8, DU1_DR5_Y7_DATA3),
528 PINMUX_IPSR_GPSR(IP1_9, DU1_DR6_DATA4),
529 PINMUX_IPSR_GPSR(IP1_10, DU1_DR7_DATA5),
530 PINMUX_IPSR_GPSR(IP1_11, DU1_DG2_C6_DATA6),
531 PINMUX_IPSR_GPSR(IP1_12, DU1_DG3_C7_DATA7),
532 PINMUX_IPSR_GPSR(IP1_13, DU1_DG4_Y0_DATA8),
533 PINMUX_IPSR_GPSR(IP1_14, DU1_DG5_Y1_DATA9),
534 PINMUX_IPSR_GPSR(IP1_15, DU1_DG6_Y2_DATA10),
535 PINMUX_IPSR_GPSR(IP1_16, DU1_DG7_Y3_DATA11),
536 PINMUX_IPSR_GPSR(IP1_17, A20),
537 PINMUX_IPSR_GPSR(IP1_17, MOSI_IO0),
538 PINMUX_IPSR_GPSR(IP1_18, A21),
539 PINMUX_IPSR_GPSR(IP1_18, MISO_IO1),
540 PINMUX_IPSR_GPSR(IP1_19, A22),
541 PINMUX_IPSR_GPSR(IP1_19, IO2),
542 PINMUX_IPSR_GPSR(IP1_20, A23),
543 PINMUX_IPSR_GPSR(IP1_20, IO3),
544 PINMUX_IPSR_GPSR(IP1_21, A24),
545 PINMUX_IPSR_GPSR(IP1_21, SPCLK),
546 PINMUX_IPSR_GPSR(IP1_22, A25),
547 PINMUX_IPSR_GPSR(IP1_22, SSL),
548
549 /* IPSR2 */
550 PINMUX_IPSR_GPSR(IP2_0, VI2_CLK),
551 PINMUX_IPSR_GPSR(IP2_0, AVB_RX_CLK),
552 PINMUX_IPSR_GPSR(IP2_1, VI2_CLKENB),
553 PINMUX_IPSR_GPSR(IP2_1, AVB_RX_DV),
554 PINMUX_IPSR_GPSR(IP2_2, VI2_HSYNC_N),
555 PINMUX_IPSR_GPSR(IP2_2, AVB_RXD0),
556 PINMUX_IPSR_GPSR(IP2_3, VI2_VSYNC_N),
557 PINMUX_IPSR_GPSR(IP2_3, AVB_RXD1),
558 PINMUX_IPSR_GPSR(IP2_4, VI2_D0_C0),
559 PINMUX_IPSR_GPSR(IP2_4, AVB_RXD2),
560 PINMUX_IPSR_GPSR(IP2_5, VI2_D1_C1),
561 PINMUX_IPSR_GPSR(IP2_5, AVB_RXD3),
562 PINMUX_IPSR_GPSR(IP2_6, VI2_D2_C2),
563 PINMUX_IPSR_GPSR(IP2_6, AVB_RXD4),
564 PINMUX_IPSR_GPSR(IP2_7, VI2_D3_C3),
565 PINMUX_IPSR_GPSR(IP2_7, AVB_RXD5),
566 PINMUX_IPSR_GPSR(IP2_8, VI2_D4_C4),
567 PINMUX_IPSR_GPSR(IP2_8, AVB_RXD6),
568 PINMUX_IPSR_GPSR(IP2_9, VI2_D5_C5),
569 PINMUX_IPSR_GPSR(IP2_9, AVB_RXD7),
570 PINMUX_IPSR_GPSR(IP2_10, VI2_D6_C6),
571 PINMUX_IPSR_GPSR(IP2_10, AVB_RX_ER),
572 PINMUX_IPSR_GPSR(IP2_11, VI2_D7_C7),
573 PINMUX_IPSR_GPSR(IP2_11, AVB_COL),
574 PINMUX_IPSR_GPSR(IP2_12, VI2_D8_Y0),
575 PINMUX_IPSR_GPSR(IP2_12, AVB_TXD3),
576 PINMUX_IPSR_GPSR(IP2_13, VI2_D9_Y1),
577 PINMUX_IPSR_GPSR(IP2_13, AVB_TX_EN),
578 PINMUX_IPSR_GPSR(IP2_14, VI2_D10_Y2),
579 PINMUX_IPSR_GPSR(IP2_14, AVB_TXD0),
580 PINMUX_IPSR_GPSR(IP2_15, VI2_D11_Y3),
581 PINMUX_IPSR_GPSR(IP2_15, AVB_TXD1),
582 PINMUX_IPSR_GPSR(IP2_16, VI2_FIELD),
583 PINMUX_IPSR_GPSR(IP2_16, AVB_TXD2),
584
585 /* IPSR3 */
586 PINMUX_IPSR_GPSR(IP3_0, VI3_CLK),
587 PINMUX_IPSR_GPSR(IP3_0, AVB_TX_CLK),
588 PINMUX_IPSR_GPSR(IP3_1, VI3_CLKENB),
589 PINMUX_IPSR_GPSR(IP3_1, AVB_TXD4),
590 PINMUX_IPSR_GPSR(IP3_2, VI3_HSYNC_N),
591 PINMUX_IPSR_GPSR(IP3_2, AVB_TXD5),
592 PINMUX_IPSR_GPSR(IP3_3, VI3_VSYNC_N),
593 PINMUX_IPSR_GPSR(IP3_3, AVB_TXD6),
594 PINMUX_IPSR_GPSR(IP3_4, VI3_D0_C0),
595 PINMUX_IPSR_GPSR(IP3_4, AVB_TXD7),
596 PINMUX_IPSR_GPSR(IP3_5, VI3_D1_C1),
597 PINMUX_IPSR_GPSR(IP3_5, AVB_TX_ER),
598 PINMUX_IPSR_GPSR(IP3_6, VI3_D2_C2),
599 PINMUX_IPSR_GPSR(IP3_6, AVB_GTX_CLK),
600 PINMUX_IPSR_GPSR(IP3_7, VI3_D3_C3),
601 PINMUX_IPSR_GPSR(IP3_7, AVB_MDC),
602 PINMUX_IPSR_GPSR(IP3_8, VI3_D4_C4),
603 PINMUX_IPSR_GPSR(IP3_8, AVB_MDIO),
604 PINMUX_IPSR_GPSR(IP3_9, VI3_D5_C5),
605 PINMUX_IPSR_GPSR(IP3_9, AVB_LINK),
606 PINMUX_IPSR_GPSR(IP3_10, VI3_D6_C6),
607 PINMUX_IPSR_GPSR(IP3_10, AVB_MAGIC),
608 PINMUX_IPSR_GPSR(IP3_11, VI3_D7_C7),
609 PINMUX_IPSR_GPSR(IP3_11, AVB_PHY_INT),
610 PINMUX_IPSR_GPSR(IP3_12, VI3_D8_Y0),
611 PINMUX_IPSR_GPSR(IP3_12, AVB_CRS),
612 PINMUX_IPSR_GPSR(IP3_13, VI3_D9_Y1),
613 PINMUX_IPSR_GPSR(IP3_13, AVB_GTXREFCLK),
614 PINMUX_IPSR_GPSR(IP3_14, VI3_D11_Y3),
615 PINMUX_IPSR_GPSR(IP3_14, AVB_AVTP_MATCH),
616
617 /* IPSR4 */
618 PINMUX_IPSR_GPSR(IP4_0, VI4_CLKENB),
619 PINMUX_IPSR_GPSR(IP4_0, VI0_D12_G4_Y4),
620 PINMUX_IPSR_GPSR(IP4_1, VI4_HSYNC_N),
621 PINMUX_IPSR_GPSR(IP4_1, VI0_D13_G5_Y5),
622 PINMUX_IPSR_GPSR(IP4_3_2, VI4_VSYNC_N),
623 PINMUX_IPSR_GPSR(IP4_3_2, VI0_D14_G6_Y6),
624 PINMUX_IPSR_GPSR(IP4_4, VI4_D0_C0),
625 PINMUX_IPSR_GPSR(IP4_4, VI0_D15_G7_Y7),
626 PINMUX_IPSR_GPSR(IP4_6_5, VI4_D1_C1),
627 PINMUX_IPSR_GPSR(IP4_6_5, VI0_D16_R0),
628 PINMUX_IPSR_MSEL(IP4_6_5, VI1_D12_G4_Y4, SEL_VI1_0),
629 PINMUX_IPSR_GPSR(IP4_8_7, VI4_D2_C2),
630 PINMUX_IPSR_GPSR(IP4_8_7, VI0_D17_R1),
631 PINMUX_IPSR_MSEL(IP4_8_7, VI1_D13_G5_Y5, SEL_VI1_0),
632 PINMUX_IPSR_GPSR(IP4_10_9, VI4_D3_C3),
633 PINMUX_IPSR_GPSR(IP4_10_9, VI0_D18_R2),
634 PINMUX_IPSR_MSEL(IP4_10_9, VI1_D14_G6_Y6, SEL_VI1_0),
635 PINMUX_IPSR_GPSR(IP4_12_11, VI4_D4_C4),
636 PINMUX_IPSR_GPSR(IP4_12_11, VI0_D19_R3),
637 PINMUX_IPSR_MSEL(IP4_12_11, VI1_D15_G7_Y7, SEL_VI1_0),
638 PINMUX_IPSR_GPSR(IP4_14_13, VI4_D5_C5),
639 PINMUX_IPSR_GPSR(IP4_14_13, VI0_D20_R4),
640 PINMUX_IPSR_GPSR(IP4_14_13, VI2_D12_Y4),
641 PINMUX_IPSR_GPSR(IP4_16_15, VI4_D6_C6),
642 PINMUX_IPSR_GPSR(IP4_16_15, VI0_D21_R5),
643 PINMUX_IPSR_GPSR(IP4_16_15, VI2_D13_Y5),
644 PINMUX_IPSR_GPSR(IP4_18_17, VI4_D7_C7),
645 PINMUX_IPSR_GPSR(IP4_18_17, VI0_D22_R6),
646 PINMUX_IPSR_GPSR(IP4_18_17, VI2_D14_Y6),
647 PINMUX_IPSR_GPSR(IP4_20_19, VI4_D8_Y0),
648 PINMUX_IPSR_GPSR(IP4_20_19, VI0_D23_R7),
649 PINMUX_IPSR_GPSR(IP4_20_19, VI2_D15_Y7),
650 PINMUX_IPSR_GPSR(IP4_21, VI4_D9_Y1),
651 PINMUX_IPSR_GPSR(IP4_21, VI3_D12_Y4),
652 PINMUX_IPSR_GPSR(IP4_22, VI4_D10_Y2),
653 PINMUX_IPSR_GPSR(IP4_22, VI3_D13_Y5),
654 PINMUX_IPSR_GPSR(IP4_23, VI4_D11_Y3),
655 PINMUX_IPSR_GPSR(IP4_23, VI3_D14_Y6),
656 PINMUX_IPSR_GPSR(IP4_24, VI4_FIELD),
657 PINMUX_IPSR_GPSR(IP4_24, VI3_D15_Y7),
658
659 /* IPSR5 */
660 PINMUX_IPSR_GPSR(IP5_0, VI5_CLKENB),
661 PINMUX_IPSR_MSEL(IP5_0, VI1_D12_G4_Y4_B, SEL_VI1_1),
662 PINMUX_IPSR_GPSR(IP5_1, VI5_HSYNC_N),
663 PINMUX_IPSR_MSEL(IP5_1, VI1_D13_G5_Y5_B, SEL_VI1_1),
664 PINMUX_IPSR_GPSR(IP5_2, VI5_VSYNC_N),
665 PINMUX_IPSR_MSEL(IP5_2, VI1_D14_G6_Y6_B, SEL_VI1_1),
666 PINMUX_IPSR_GPSR(IP5_3, VI5_D0_C0),
667 PINMUX_IPSR_MSEL(IP5_3, VI1_D15_G7_Y7_B, SEL_VI1_1),
668 PINMUX_IPSR_GPSR(IP5_4, VI5_D1_C1),
669 PINMUX_IPSR_GPSR(IP5_4, VI1_D16_R0),
670 PINMUX_IPSR_GPSR(IP5_5, VI5_D2_C2),
671 PINMUX_IPSR_GPSR(IP5_5, VI1_D17_R1),
672 PINMUX_IPSR_GPSR(IP5_6, VI5_D3_C3),
673 PINMUX_IPSR_GPSR(IP5_6, VI1_D18_R2),
674 PINMUX_IPSR_GPSR(IP5_7, VI5_D4_C4),
675 PINMUX_IPSR_GPSR(IP5_7, VI1_D19_R3),
676 PINMUX_IPSR_GPSR(IP5_8, VI5_D5_C5),
677 PINMUX_IPSR_GPSR(IP5_8, VI1_D20_R4),
678 PINMUX_IPSR_GPSR(IP5_9, VI5_D6_C6),
679 PINMUX_IPSR_GPSR(IP5_9, VI1_D21_R5),
680 PINMUX_IPSR_GPSR(IP5_10, VI5_D7_C7),
681 PINMUX_IPSR_GPSR(IP5_10, VI1_D22_R6),
682 PINMUX_IPSR_GPSR(IP5_11, VI5_D8_Y0),
683 PINMUX_IPSR_GPSR(IP5_11, VI1_D23_R7),
684
685 /* IPSR6 */
686 PINMUX_IPSR_GPSR(IP6_0, MSIOF0_SCK),
687 PINMUX_IPSR_GPSR(IP6_0, HSCK0),
688 PINMUX_IPSR_GPSR(IP6_1, MSIOF0_SYNC),
689 PINMUX_IPSR_GPSR(IP6_1, HCTS0_N),
690 PINMUX_IPSR_GPSR(IP6_2, MSIOF0_TXD),
691 PINMUX_IPSR_GPSR(IP6_2, HTX0),
692 PINMUX_IPSR_GPSR(IP6_3, MSIOF0_RXD),
693 PINMUX_IPSR_GPSR(IP6_3, HRX0),
694 PINMUX_IPSR_GPSR(IP6_4, MSIOF1_SCK),
695 PINMUX_IPSR_GPSR(IP6_4, HSCK1),
696 PINMUX_IPSR_GPSR(IP6_5, MSIOF1_SYNC),
697 PINMUX_IPSR_GPSR(IP6_5, HRTS1_N),
698 PINMUX_IPSR_GPSR(IP6_6, MSIOF1_TXD),
699 PINMUX_IPSR_GPSR(IP6_6, HTX1),
700 PINMUX_IPSR_GPSR(IP6_7, MSIOF1_RXD),
701 PINMUX_IPSR_GPSR(IP6_7, HRX1),
702 PINMUX_IPSR_GPSR(IP6_9_8, DRACK0),
703 PINMUX_IPSR_GPSR(IP6_9_8, SCK2),
704 PINMUX_IPSR_GPSR(IP6_11_10, DACK0),
705 PINMUX_IPSR_GPSR(IP6_11_10, TX2),
706 PINMUX_IPSR_GPSR(IP6_13_12, DREQ0_N),
707 PINMUX_IPSR_GPSR(IP6_13_12, RX2),
708 PINMUX_IPSR_GPSR(IP6_15_14, DACK1),
709 PINMUX_IPSR_GPSR(IP6_15_14, SCK3),
710 PINMUX_IPSR_GPSR(IP6_16, TX3),
711 PINMUX_IPSR_GPSR(IP6_18_17, DREQ1_N),
712 PINMUX_IPSR_GPSR(IP6_18_17, RX3),
713
714 /* IPSR7 */
715 PINMUX_IPSR_GPSR(IP7_1_0, PWM0),
716 PINMUX_IPSR_GPSR(IP7_1_0, TCLK1),
717 PINMUX_IPSR_GPSR(IP7_1_0, FSO_CFE_0),
718 PINMUX_IPSR_GPSR(IP7_3_2, PWM1),
719 PINMUX_IPSR_GPSR(IP7_3_2, TCLK2),
720 PINMUX_IPSR_GPSR(IP7_3_2, FSO_CFE_1),
721 PINMUX_IPSR_GPSR(IP7_5_4, PWM2),
722 PINMUX_IPSR_GPSR(IP7_5_4, TCLK3),
723 PINMUX_IPSR_GPSR(IP7_5_4, FSO_TOE),
724 PINMUX_IPSR_GPSR(IP7_6, PWM3),
725 PINMUX_IPSR_GPSR(IP7_7, PWM4),
726 PINMUX_IPSR_GPSR(IP7_9_8, SSI_SCK34),
727 PINMUX_IPSR_GPSR(IP7_9_8, TPU0TO0),
728 PINMUX_IPSR_GPSR(IP7_11_10, SSI_WS34),
729 PINMUX_IPSR_GPSR(IP7_11_10, TPU0TO1),
730 PINMUX_IPSR_GPSR(IP7_13_12, SSI_SDATA3),
731 PINMUX_IPSR_GPSR(IP7_13_12, TPU0TO2),
732 PINMUX_IPSR_GPSR(IP7_15_14, SSI_SCK4),
733 PINMUX_IPSR_GPSR(IP7_15_14, TPU0TO3),
734 PINMUX_IPSR_GPSR(IP7_16, SSI_WS4),
735 PINMUX_IPSR_GPSR(IP7_17, SSI_SDATA4),
736 PINMUX_IPSR_GPSR(IP7_18, AUDIO_CLKOUT),
737 PINMUX_IPSR_GPSR(IP7_19, AUDIO_CLKA),
738 PINMUX_IPSR_GPSR(IP7_20, AUDIO_CLKB),
739};
740
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]741/*
742 * Pins not associated with a GPIO port.
743 */
744enum {
745 GP_ASSIGN_LAST(),
746 NOGP_ALL(),
747};
748
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]749static const struct sh_pfc_pin pinmux_pins[] = {
750 PINMUX_GPIO_GP_ALL(),
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]751 PINMUX_NOGP_ALL(),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]752};
753
754/* - AVB -------------------------------------------------------------------- */
755static const unsigned int avb_link_pins[] = {
756 RCAR_GP_PIN(7, 9),
757};
758static const unsigned int avb_link_mux[] = {
759 AVB_LINK_MARK,
760};
761static const unsigned int avb_magic_pins[] = {
762 RCAR_GP_PIN(7, 10),
763};
764static const unsigned int avb_magic_mux[] = {
765 AVB_MAGIC_MARK,
766};
767static const unsigned int avb_phy_int_pins[] = {
768 RCAR_GP_PIN(7, 11),
769};
770static const unsigned int avb_phy_int_mux[] = {
771 AVB_PHY_INT_MARK,
772};
773static const unsigned int avb_mdio_pins[] = {
774 RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8),
775};
776static const unsigned int avb_mdio_mux[] = {
777 AVB_MDC_MARK, AVB_MDIO_MARK,
778};
779static const unsigned int avb_mii_pins[] = {
780 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 16),
781 RCAR_GP_PIN(6, 12),
782
783 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4),
784 RCAR_GP_PIN(6, 5),
785
786 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
787 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(6, 13), RCAR_GP_PIN(7, 5),
788 RCAR_GP_PIN(7, 0), RCAR_GP_PIN(6, 11),
789};
790static const unsigned int avb_mii_mux[] = {
791 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
792 AVB_TXD3_MARK,
793
794 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
795 AVB_RXD3_MARK,
796
797 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
798 AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
799 AVB_TX_CLK_MARK, AVB_COL_MARK,
800};
801static const unsigned int avb_gmii_pins[] = {
802 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 16),
803 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 2),
804 RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
805
806 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4),
807 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
808 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
809
810 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
811 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 13),
812 RCAR_GP_PIN(6, 13), RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 0),
813 RCAR_GP_PIN(6, 11),
814};
815static const unsigned int avb_gmii_mux[] = {
816 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
817 AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
818 AVB_TXD6_MARK, AVB_TXD7_MARK,
819
820 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
821 AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
822 AVB_RXD6_MARK, AVB_RXD7_MARK,
823
824 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
825 AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
826 AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
827 AVB_COL_MARK,
828};
829static const unsigned int avb_avtp_match_pins[] = {
830 RCAR_GP_PIN(7, 15),
831};
832static const unsigned int avb_avtp_match_mux[] = {
833 AVB_AVTP_MATCH_MARK,
834};
835/* - CAN -------------------------------------------------------------------- */
836static const unsigned int can0_data_pins[] = {
837 /* TX, RX */
838 RCAR_GP_PIN(10, 27), RCAR_GP_PIN(10, 28),
839};
840static const unsigned int can0_data_mux[] = {
841 CAN0_TX_MARK, CAN0_RX_MARK,
842};
843static const unsigned int can1_data_pins[] = {
844 /* TX, RX */
845 RCAR_GP_PIN(10, 30), RCAR_GP_PIN(10, 31),
846};
847static const unsigned int can1_data_mux[] = {
848 CAN1_TX_MARK, CAN1_RX_MARK,
849};
850static const unsigned int can_clk_pins[] = {
851 /* CAN_CLK */
852 RCAR_GP_PIN(10, 29),
853};
854static const unsigned int can_clk_mux[] = {
855 CAN_CLK_MARK,
856};
857/* - DU --------------------------------------------------------------------- */
858static const unsigned int du0_rgb666_pins[] = {
859 /* R[7:2], G[7:2], B[7:2] */
860 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
861 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2),
862 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
863 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
864 RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
865 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 18),
866};
867static const unsigned int du0_rgb666_mux[] = {
868 DU0_DR7_Y9_DATA7_MARK, DU0_DR6_Y8_DATA6_MARK, DU0_DR5_Y7_DATA5_MARK,
869 DU0_DR4_Y6_DATA4_MARK, DU0_DR3_Y5_DATA3_MARK, DU0_DR2_Y4_DATA2_MARK,
870 DU0_DG7_Y3_DATA15_MARK, DU0_DG6_Y2_DATA14_MARK, DU0_DG5_Y1_DATA13_MARK,
871 DU0_DG4_Y0_DATA12_MARK, DU0_DG3_C7_DATA11_MARK, DU0_DG2_C6_DATA10_MARK,
872 DU0_DB7_C5_MARK, DU0_DB6_C4_MARK, DU0_DB5_C3_MARK,
873 DU0_DB4_C2_MARK, DU0_DB3_C1_MARK, DU0_DB2_C0_MARK,
874};
875static const unsigned int du0_rgb888_pins[] = {
876 /* R[7:0], G[7:0], B[7:0] */
877 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
878 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2),
879 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
880 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
881 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
882 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
883 RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
884 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 18),
885 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
886};
887static const unsigned int du0_rgb888_mux[] = {
888 DU0_DR7_Y9_DATA7_MARK, DU0_DR6_Y8_DATA6_MARK, DU0_DR5_Y7_DATA5_MARK,
889 DU0_DR4_Y6_DATA4_MARK, DU0_DR3_Y5_DATA3_MARK, DU0_DR2_Y4_DATA2_MARK,
890 DU0_DR1_DATA1_MARK, DU0_DR0_DATA0_MARK,
891 DU0_DG7_Y3_DATA15_MARK, DU0_DG6_Y2_DATA14_MARK, DU0_DG5_Y1_DATA13_MARK,
892 DU0_DG4_Y0_DATA12_MARK, DU0_DG3_C7_DATA11_MARK, DU0_DG2_C6_DATA10_MARK,
893 DU0_DG1_DATA9_MARK, DU0_DG0_DATA8_MARK,
894 DU0_DB7_C5_MARK, DU0_DB6_C4_MARK, DU0_DB5_C3_MARK,
895 DU0_DB4_C2_MARK, DU0_DB3_C1_MARK, DU0_DB2_C0_MARK,
896 DU0_DB1_MARK, DU0_DB0_MARK,
897};
898static const unsigned int du0_sync_pins[] = {
899 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
900 RCAR_GP_PIN(0, 25), RCAR_GP_PIN(0, 24),
901};
902static const unsigned int du0_sync_mux[] = {
903 DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK,
904};
905static const unsigned int du0_oddf_pins[] = {
906 /* EXODDF/ODDF/DISP/CDE */
907 RCAR_GP_PIN(0, 26),
908};
909static const unsigned int du0_oddf_mux[] = {
910 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
911};
912static const unsigned int du0_disp_pins[] = {
913 /* DISP */
914 RCAR_GP_PIN(0, 27),
915};
916static const unsigned int du0_disp_mux[] = {
917 DU0_DISP_MARK,
918};
919static const unsigned int du0_cde_pins[] = {
920 /* CDE */
921 RCAR_GP_PIN(0, 28),
922};
923static const unsigned int du0_cde_mux[] = {
924 DU0_CDE_MARK,
925};
926static const unsigned int du1_rgb666_pins[] = {
927 /* R[7:2], G[7:2], B[7:2] */
928 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
929 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
930 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
931 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
932 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15),
933 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12),
934};
935static const unsigned int du1_rgb666_mux[] = {
936 DU1_DR7_DATA5_MARK, DU1_DR6_DATA4_MARK, DU1_DR5_Y7_DATA3_MARK,
937 DU1_DR4_Y6_DATA2_MARK, DU1_DR3_Y5_DATA1_MARK, DU1_DR2_Y4_DATA0_MARK,
938 DU1_DG7_Y3_DATA11_MARK, DU1_DG6_Y2_DATA10_MARK, DU1_DG5_Y1_DATA9_MARK,
939 DU1_DG4_Y0_DATA8_MARK, DU1_DG3_C7_DATA7_MARK, DU1_DG2_C6_DATA6_MARK,
940 DU1_DB7_C5_MARK, DU1_DB6_C4_MARK, DU1_DB5_C3_DATA15_MARK,
941 DU1_DB4_C2_DATA14_MARK, DU1_DB3_C1_DATA13_MARK, DU1_DB2_C0_DATA12_MARK,
942};
943static const unsigned int du1_sync_pins[] = {
944 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
945 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
946};
947static const unsigned int du1_sync_mux[] = {
948 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
949};
950static const unsigned int du1_oddf_pins[] = {
951 /* EXODDF/ODDF/DISP/CDE */
952 RCAR_GP_PIN(1, 20),
953};
954static const unsigned int du1_oddf_mux[] = {
955 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
956};
957static const unsigned int du1_disp_pins[] = {
958 /* DISP */
959 RCAR_GP_PIN(1, 21),
960};
961static const unsigned int du1_disp_mux[] = {
962 DU1_DISP_MARK,
963};
964static const unsigned int du1_cde_pins[] = {
965 /* CDE */
966 RCAR_GP_PIN(1, 22),
967};
968static const unsigned int du1_cde_mux[] = {
969 DU1_CDE_MARK,
970};
971/* - INTC ------------------------------------------------------------------- */
972static const unsigned int intc_irq0_pins[] = {
973 /* IRQ0 */
974 RCAR_GP_PIN(3, 19),
975};
976static const unsigned int intc_irq0_mux[] = {
977 IRQ0_MARK,
978};
979static const unsigned int intc_irq1_pins[] = {
980 /* IRQ1 */
981 RCAR_GP_PIN(3, 20),
982};
983static const unsigned int intc_irq1_mux[] = {
984 IRQ1_MARK,
985};
986static const unsigned int intc_irq2_pins[] = {
987 /* IRQ2 */
988 RCAR_GP_PIN(3, 21),
989};
990static const unsigned int intc_irq2_mux[] = {
991 IRQ2_MARK,
992};
993static const unsigned int intc_irq3_pins[] = {
994 /* IRQ3 */
995 RCAR_GP_PIN(3, 22),
996};
997static const unsigned int intc_irq3_mux[] = {
998 IRQ3_MARK,
999};
1000/* - LBSC ------------------------------------------------------------------- */
1001static const unsigned int lbsc_cs0_pins[] = {
1002 /* CS0# */
1003 RCAR_GP_PIN(3, 27),
1004};
1005static const unsigned int lbsc_cs0_mux[] = {
1006 CS0_N_MARK,
1007};
1008static const unsigned int lbsc_cs1_pins[] = {
1009 /* CS1#_A26 */
1010 RCAR_GP_PIN(3, 6),
1011};
1012static const unsigned int lbsc_cs1_mux[] = {
1013 CS1_N_A26_MARK,
1014};
1015static const unsigned int lbsc_ex_cs0_pins[] = {
1016 /* EX_CS0# */
1017 RCAR_GP_PIN(3, 7),
1018};
1019static const unsigned int lbsc_ex_cs0_mux[] = {
1020 EX_CS0_N_MARK,
1021};
1022static const unsigned int lbsc_ex_cs1_pins[] = {
1023 /* EX_CS1# */
1024 RCAR_GP_PIN(3, 8),
1025};
1026static const unsigned int lbsc_ex_cs1_mux[] = {
1027 EX_CS1_N_MARK,
1028};
1029static const unsigned int lbsc_ex_cs2_pins[] = {
1030 /* EX_CS2# */
1031 RCAR_GP_PIN(3, 9),
1032};
1033static const unsigned int lbsc_ex_cs2_mux[] = {
1034 EX_CS2_N_MARK,
1035};
1036static const unsigned int lbsc_ex_cs3_pins[] = {
1037 /* EX_CS3# */
1038 RCAR_GP_PIN(3, 10),
1039};
1040static const unsigned int lbsc_ex_cs3_mux[] = {
1041 EX_CS3_N_MARK,
1042};
1043static const unsigned int lbsc_ex_cs4_pins[] = {
1044 /* EX_CS4# */
1045 RCAR_GP_PIN(3, 11),
1046};
1047static const unsigned int lbsc_ex_cs4_mux[] = {
1048 EX_CS4_N_MARK,
1049};
1050static const unsigned int lbsc_ex_cs5_pins[] = {
1051 /* EX_CS5# */
1052 RCAR_GP_PIN(3, 12),
1053};
1054static const unsigned int lbsc_ex_cs5_mux[] = {
1055 EX_CS5_N_MARK,
1056};
1057/* - MSIOF0 ----------------------------------------------------------------- */
1058static const unsigned int msiof0_clk_pins[] = {
1059 /* SCK */
1060 RCAR_GP_PIN(10, 0),
1061};
1062static const unsigned int msiof0_clk_mux[] = {
1063 MSIOF0_SCK_MARK,
1064};
1065static const unsigned int msiof0_sync_pins[] = {
1066 /* SYNC */
1067 RCAR_GP_PIN(10, 1),
1068};
1069static const unsigned int msiof0_sync_mux[] = {
1070 MSIOF0_SYNC_MARK,
1071};
1072static const unsigned int msiof0_rx_pins[] = {
1073 /* RXD */
1074 RCAR_GP_PIN(10, 4),
1075};
1076static const unsigned int msiof0_rx_mux[] = {
1077 MSIOF0_RXD_MARK,
1078};
1079static const unsigned int msiof0_tx_pins[] = {
1080 /* TXD */
1081 RCAR_GP_PIN(10, 3),
1082};
1083static const unsigned int msiof0_tx_mux[] = {
1084 MSIOF0_TXD_MARK,
1085};
1086/* - MSIOF1 ----------------------------------------------------------------- */
1087static const unsigned int msiof1_clk_pins[] = {
1088 /* SCK */
1089 RCAR_GP_PIN(10, 5),
1090};
1091static const unsigned int msiof1_clk_mux[] = {
1092 MSIOF1_SCK_MARK,
1093};
1094static const unsigned int msiof1_sync_pins[] = {
1095 /* SYNC */
1096 RCAR_GP_PIN(10, 6),
1097};
1098static const unsigned int msiof1_sync_mux[] = {
1099 MSIOF1_SYNC_MARK,
1100};
1101static const unsigned int msiof1_rx_pins[] = {
1102 /* RXD */
1103 RCAR_GP_PIN(10, 9),
1104};
1105static const unsigned int msiof1_rx_mux[] = {
1106 MSIOF1_RXD_MARK,
1107};
1108static const unsigned int msiof1_tx_pins[] = {
1109 /* TXD */
1110 RCAR_GP_PIN(10, 8),
1111};
1112static const unsigned int msiof1_tx_mux[] = {
1113 MSIOF1_TXD_MARK,
1114};
1115/* - QSPI ------------------------------------------------------------------- */
1116static const unsigned int qspi_ctrl_pins[] = {
1117 /* SPCLK, SSL */
1118 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
1119};
1120static const unsigned int qspi_ctrl_mux[] = {
1121 SPCLK_MARK, SSL_MARK,
1122};
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1123static const unsigned int qspi_data_pins[] = {
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1124 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
1125 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 23),
1126 RCAR_GP_PIN(3, 24),
1127};
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1128static const unsigned int qspi_data_mux[] = {
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1129 MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
1130};
1131/* - SCIF0 ------------------------------------------------------------------ */
1132static const unsigned int scif0_data_pins[] = {
1133 /* RX, TX */
1134 RCAR_GP_PIN(10, 14), RCAR_GP_PIN(10, 13),
1135};
1136static const unsigned int scif0_data_mux[] = {
1137 RX0_MARK, TX0_MARK,
1138};
1139static const unsigned int scif0_clk_pins[] = {
1140 /* SCK */
1141 RCAR_GP_PIN(10, 10),
1142};
1143static const unsigned int scif0_clk_mux[] = {
1144 SCK0_MARK,
1145};
1146static const unsigned int scif0_ctrl_pins[] = {
1147 /* RTS, CTS */
1148 RCAR_GP_PIN(10, 12), RCAR_GP_PIN(10, 11),
1149};
1150static const unsigned int scif0_ctrl_mux[] = {
1151 RTS0_N_MARK, CTS0_N_MARK,
1152};
1153/* - SCIF1 ------------------------------------------------------------------ */
1154static const unsigned int scif1_data_pins[] = {
1155 /* RX, TX */
1156 RCAR_GP_PIN(10, 19), RCAR_GP_PIN(10, 18),
1157};
1158static const unsigned int scif1_data_mux[] = {
1159 RX1_MARK, TX1_MARK,
1160};
1161static const unsigned int scif1_clk_pins[] = {
1162 /* SCK */
1163 RCAR_GP_PIN(10, 15),
1164};
1165static const unsigned int scif1_clk_mux[] = {
1166 SCK1_MARK,
1167};
1168static const unsigned int scif1_ctrl_pins[] = {
1169 /* RTS, CTS */
1170 RCAR_GP_PIN(10, 17), RCAR_GP_PIN(10, 16),
1171};
1172static const unsigned int scif1_ctrl_mux[] = {
1173 RTS1_N_MARK, CTS1_N_MARK,
1174};
1175/* - SCIF2 ------------------------------------------------------------------ */
1176static const unsigned int scif2_data_pins[] = {
1177 /* RX, TX */
1178 RCAR_GP_PIN(10, 22), RCAR_GP_PIN(10, 21),
1179};
1180static const unsigned int scif2_data_mux[] = {
1181 RX2_MARK, TX2_MARK,
1182};
1183static const unsigned int scif2_clk_pins[] = {
1184 /* SCK */
1185 RCAR_GP_PIN(10, 20),
1186};
1187static const unsigned int scif2_clk_mux[] = {
1188 SCK2_MARK,
1189};
1190/* - SCIF3 ------------------------------------------------------------------ */
1191static const unsigned int scif3_data_pins[] = {
1192 /* RX, TX */
1193 RCAR_GP_PIN(10, 25), RCAR_GP_PIN(10, 24),
1194};
1195static const unsigned int scif3_data_mux[] = {
1196 RX3_MARK, TX3_MARK,
1197};
1198static const unsigned int scif3_clk_pins[] = {
1199 /* SCK */
1200 RCAR_GP_PIN(10, 23),
1201};
1202static const unsigned int scif3_clk_mux[] = {
1203 SCK3_MARK,
1204};
1205/* - SDHI0 ------------------------------------------------------------------ */
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1206static const unsigned int sdhi0_data_pins[] = {
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1207 /* DAT[0-3] */
1208 RCAR_GP_PIN(11, 7), RCAR_GP_PIN(11, 8),
1209 RCAR_GP_PIN(11, 9), RCAR_GP_PIN(11, 10),
1210};
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1211static const unsigned int sdhi0_data_mux[] = {
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1212 SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
1213};
1214static const unsigned int sdhi0_ctrl_pins[] = {
1215 /* CLK, CMD */
1216 RCAR_GP_PIN(11, 5), RCAR_GP_PIN(11, 6),
1217};
1218static const unsigned int sdhi0_ctrl_mux[] = {
1219 SD0_CLK_MARK, SD0_CMD_MARK,
1220};
1221static const unsigned int sdhi0_cd_pins[] = {
1222 /* CD */
1223 RCAR_GP_PIN(11, 11),
1224};
1225static const unsigned int sdhi0_cd_mux[] = {
1226 SD0_CD_MARK,
1227};
1228static const unsigned int sdhi0_wp_pins[] = {
1229 /* WP */
1230 RCAR_GP_PIN(11, 12),
1231};
1232static const unsigned int sdhi0_wp_mux[] = {
1233 SD0_WP_MARK,
1234};
1235/* - VIN0 ------------------------------------------------------------------- */
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1236static const unsigned int vin0_data_pins[] = {
1237 /* B */
1238 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1239 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1240 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1241 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1242 /* G */
1243 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
1244 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
1245 RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),
1246 RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),
1247 /* R */
1248 RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1249 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1250 RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1251 RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1252};
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1253static const unsigned int vin0_data_mux[] = {
1254 /* B */
1255 VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK,
1256 VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
1257 VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
1258 VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
1259 /* G */
1260 VI0_D8_G0_Y0_MARK, VI0_D9_G1_Y1_MARK,
1261 VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
1262 VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,
1263 VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,
1264 /* R */
1265 VI0_D16_R0_MARK, VI0_D17_R1_MARK,
1266 VI0_D18_R2_MARK, VI0_D19_R3_MARK,
1267 VI0_D20_R4_MARK, VI0_D21_R5_MARK,
1268 VI0_D22_R6_MARK, VI0_D23_R7_MARK,
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1269};
1270static const unsigned int vin0_data18_pins[] = {
1271 /* B */
1272 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1273 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1274 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1275 /* G */
1276 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
1277 RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),
1278 RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),
1279 /* R */
1280 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1281 RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1282 RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
1283};
1284static const unsigned int vin0_data18_mux[] = {
1285 /* B */
1286 VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
1287 VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
1288 VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
1289 /* G */
1290 VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
1291 VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,
1292 VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,
1293 /* R */
1294 VI0_D18_R2_MARK, VI0_D19_R3_MARK,
1295 VI0_D20_R4_MARK, VI0_D21_R5_MARK,
1296 VI0_D22_R6_MARK, VI0_D23_R7_MARK,
1297};
1298static const unsigned int vin0_sync_pins[] = {
1299 /* HSYNC#, VSYNC# */
1300 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1301};
1302static const unsigned int vin0_sync_mux[] = {
1303 VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
1304};
1305static const unsigned int vin0_field_pins[] = {
1306 RCAR_GP_PIN(4, 16),
1307};
1308static const unsigned int vin0_field_mux[] = {
1309 VI0_FIELD_MARK,
1310};
1311static const unsigned int vin0_clkenb_pins[] = {
1312 RCAR_GP_PIN(4, 1),
1313};
1314static const unsigned int vin0_clkenb_mux[] = {
1315 VI0_CLKENB_MARK,
1316};
1317static const unsigned int vin0_clk_pins[] = {
1318 RCAR_GP_PIN(4, 0),
1319};
1320static const unsigned int vin0_clk_mux[] = {
1321 VI0_CLK_MARK,
1322};
1323/* - VIN1 ------------------------------------------------------------------- */
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1324static const unsigned int vin1_data_pins[] = {
1325 /* B */
1326 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1327 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1328 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1329 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1330 /* G */
1331 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
1332 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1333 RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1334 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1335 /* R */
1336 RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
1337 RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1338 RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1339 RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1340};
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1341static const unsigned int vin1_data_mux[] = {
1342 /* B */
1343 VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
1344 VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1345 VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1346 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1347 /* G */
1348 VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
1349 VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1350 VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,
1351 VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,
1352 /* R */
1353 VI1_D16_R0_MARK, VI1_D17_R1_MARK,
1354 VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1355 VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1356 VI1_D22_R6_MARK, VI1_D23_R7_MARK,
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1357};
1358static const unsigned int vin1_data18_pins[] = {
1359 /* B */
1360 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1361 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1362 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1363 /* G */
1364 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1365 RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1366 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1367 /* R */
1368 RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1369 RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1370 RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1371};
1372static const unsigned int vin1_data18_mux[] = {
1373 /* B */
1374 VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1375 VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1376 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1377 /* G */
1378 VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1379 VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,
1380 VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,
1381 /* R */
1382 VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1383 VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1384 VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1385};
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1386static const unsigned int vin1_data_b_pins[] = {
1387 /* B */
1388 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1389 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1390 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1391 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1392 /* G */
1393 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
1394 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1395 RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),
1396 RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),
1397 /* R */
1398 RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
1399 RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1400 RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1401 RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1402};
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1403static const unsigned int vin1_data_b_mux[] = {
1404 /* B */
1405 VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
1406 VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1407 VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1408 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1409 /* G */
1410 VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
1411 VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1412 VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,
1413 VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,
1414 /* R */
1415 VI1_D16_R0_MARK, VI1_D17_R1_MARK,
1416 VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1417 VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1418 VI1_D22_R6_MARK, VI1_D23_R7_MARK,
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1419};
1420static const unsigned int vin1_data18_b_pins[] = {
1421 /* B */
1422 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1423 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1424 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1425 /* G */
1426 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1427 RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),
1428 RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),
1429 /* R */
1430 RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1431 RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1432 RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1433};
1434static const unsigned int vin1_data18_b_mux[] = {
1435 /* B */
1436 VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1437 VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1438 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1439 /* G */
1440 VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1441 VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,
1442 VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,
1443 /* R */
1444 VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1445 VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1446 VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1447};
1448static const unsigned int vin1_sync_pins[] = {
1449 /* HSYNC#, VSYNC# */
1450 RCAR_GP_PIN(5, 2), RCAR_GP_PIN(5, 3),
1451};
1452static const unsigned int vin1_sync_mux[] = {
1453 VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
1454};
1455static const unsigned int vin1_field_pins[] = {
1456 RCAR_GP_PIN(5, 16),
1457};
1458static const unsigned int vin1_field_mux[] = {
1459 VI1_FIELD_MARK,
1460};
1461static const unsigned int vin1_clkenb_pins[] = {
1462 RCAR_GP_PIN(5, 1),
1463};
1464static const unsigned int vin1_clkenb_mux[] = {
1465 VI1_CLKENB_MARK,
1466};
1467static const unsigned int vin1_clk_pins[] = {
1468 RCAR_GP_PIN(5, 0),
1469};
1470static const unsigned int vin1_clk_mux[] = {
1471 VI1_CLK_MARK,
1472};
1473/* - VIN2 ------------------------------------------------------------------- */
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1474static const unsigned int vin2_data_pins[] = {
1475 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
1476 RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
1477 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1478 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
1479 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
1480 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
1481 RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1482 RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1483};
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1484static const unsigned int vin2_data_mux[] = {
1485 VI2_D0_C0_MARK, VI2_D1_C1_MARK,
1486 VI2_D2_C2_MARK, VI2_D3_C3_MARK,
1487 VI2_D4_C4_MARK, VI2_D5_C5_MARK,
1488 VI2_D6_C6_MARK, VI2_D7_C7_MARK,
1489 VI2_D8_Y0_MARK, VI2_D9_Y1_MARK,
1490 VI2_D10_Y2_MARK, VI2_D11_Y3_MARK,
1491 VI2_D12_Y4_MARK, VI2_D13_Y5_MARK,
1492 VI2_D14_Y6_MARK, VI2_D15_Y7_MARK,
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1493};
1494static const unsigned int vin2_sync_pins[] = {
1495 /* HSYNC#, VSYNC# */
1496 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
1497};
1498static const unsigned int vin2_sync_mux[] = {
1499 VI2_HSYNC_N_MARK, VI2_VSYNC_N_MARK,
1500};
1501static const unsigned int vin2_field_pins[] = {
1502 RCAR_GP_PIN(6, 16),
1503};
1504static const unsigned int vin2_field_mux[] = {
1505 VI2_FIELD_MARK,
1506};
1507static const unsigned int vin2_clkenb_pins[] = {
1508 RCAR_GP_PIN(6, 1),
1509};
1510static const unsigned int vin2_clkenb_mux[] = {
1511 VI2_CLKENB_MARK,
1512};
1513static const unsigned int vin2_clk_pins[] = {
1514 RCAR_GP_PIN(6, 0),
1515};
1516static const unsigned int vin2_clk_mux[] = {
1517 VI2_CLK_MARK,
1518};
1519/* - VIN3 ------------------------------------------------------------------- */
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1520static const unsigned int vin3_data_pins[] = {
1521 RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5),
1522 RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7),
1523 RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
1524 RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11),
1525 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 13),
1526 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
1527 RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 14),
1528 RCAR_GP_PIN(8, 15), RCAR_GP_PIN(8, 16),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1529};
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1530static const unsigned int vin3_data_mux[] = {
1531 VI3_D0_C0_MARK, VI3_D1_C1_MARK,
1532 VI3_D2_C2_MARK, VI3_D3_C3_MARK,
1533 VI3_D4_C4_MARK, VI3_D5_C5_MARK,
1534 VI3_D6_C6_MARK, VI3_D7_C7_MARK,
1535 VI3_D8_Y0_MARK, VI3_D9_Y1_MARK,
1536 VI3_D10_Y2_MARK, VI3_D11_Y3_MARK,
1537 VI3_D12_Y4_MARK, VI3_D13_Y5_MARK,
1538 VI3_D14_Y6_MARK, VI3_D15_Y7_MARK,
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1539};
1540static const unsigned int vin3_sync_pins[] = {
1541 /* HSYNC#, VSYNC# */
1542 RCAR_GP_PIN(7, 2), RCAR_GP_PIN(7, 3),
1543};
1544static const unsigned int vin3_sync_mux[] = {
1545 VI3_HSYNC_N_MARK, VI3_VSYNC_N_MARK,
1546};
1547static const unsigned int vin3_field_pins[] = {
1548 RCAR_GP_PIN(7, 16),
1549};
1550static const unsigned int vin3_field_mux[] = {
1551 VI3_FIELD_MARK,
1552};
1553static const unsigned int vin3_clkenb_pins[] = {
1554 RCAR_GP_PIN(7, 1),
1555};
1556static const unsigned int vin3_clkenb_mux[] = {
1557 VI3_CLKENB_MARK,
1558};
1559static const unsigned int vin3_clk_pins[] = {
1560 RCAR_GP_PIN(7, 0),
1561};
1562static const unsigned int vin3_clk_mux[] = {
1563 VI3_CLK_MARK,
1564};
1565/* - VIN4 ------------------------------------------------------------------- */
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1566static const unsigned int vin4_data_pins[] = {
1567 RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5),
1568 RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7),
1569 RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
1570 RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11),
1571 RCAR_GP_PIN(8, 12), RCAR_GP_PIN(8, 13),
1572 RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 15),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1573};
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1574static const unsigned int vin4_data_mux[] = {
1575 VI4_D0_C0_MARK, VI4_D1_C1_MARK,
1576 VI4_D2_C2_MARK, VI4_D3_C3_MARK,
1577 VI4_D4_C4_MARK, VI4_D5_C5_MARK,
1578 VI4_D6_C6_MARK, VI4_D7_C7_MARK,
1579 VI4_D8_Y0_MARK, VI4_D9_Y1_MARK,
1580 VI4_D10_Y2_MARK, VI4_D11_Y3_MARK,
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1581};
1582static const unsigned int vin4_sync_pins[] = {
1583 /* HSYNC#, VSYNC# */
1584 RCAR_GP_PIN(8, 2), RCAR_GP_PIN(8, 3),
1585};
1586static const unsigned int vin4_sync_mux[] = {
1587 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
1588};
1589static const unsigned int vin4_field_pins[] = {
1590 RCAR_GP_PIN(8, 16),
1591};
1592static const unsigned int vin4_field_mux[] = {
1593 VI4_FIELD_MARK,
1594};
1595static const unsigned int vin4_clkenb_pins[] = {
1596 RCAR_GP_PIN(8, 1),
1597};
1598static const unsigned int vin4_clkenb_mux[] = {
1599 VI4_CLKENB_MARK,
1600};
1601static const unsigned int vin4_clk_pins[] = {
1602 RCAR_GP_PIN(8, 0),
1603};
1604static const unsigned int vin4_clk_mux[] = {
1605 VI4_CLK_MARK,
1606};
1607/* - VIN5 ------------------------------------------------------------------- */
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1608static const unsigned int vin5_data_pins[] = {
1609 RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5),
1610 RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7),
1611 RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9),
1612 RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11),
1613 RCAR_GP_PIN(9, 12), RCAR_GP_PIN(9, 13),
1614 RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 15),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1615};
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1616static const unsigned int vin5_data_mux[] = {
1617 VI5_D0_C0_MARK, VI5_D1_C1_MARK,
1618 VI5_D2_C2_MARK, VI5_D3_C3_MARK,
1619 VI5_D4_C4_MARK, VI5_D5_C5_MARK,
1620 VI5_D6_C6_MARK, VI5_D7_C7_MARK,
1621 VI5_D8_Y0_MARK, VI5_D9_Y1_MARK,
1622 VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1623};
1624static const unsigned int vin5_sync_pins[] = {
1625 /* HSYNC#, VSYNC# */
1626 RCAR_GP_PIN(9, 2), RCAR_GP_PIN(9, 3),
1627};
1628static const unsigned int vin5_sync_mux[] = {
1629 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
1630};
1631static const unsigned int vin5_field_pins[] = {
1632 RCAR_GP_PIN(9, 16),
1633};
1634static const unsigned int vin5_field_mux[] = {
1635 VI5_FIELD_MARK,
1636};
1637static const unsigned int vin5_clkenb_pins[] = {
1638 RCAR_GP_PIN(9, 1),
1639};
1640static const unsigned int vin5_clkenb_mux[] = {
1641 VI5_CLKENB_MARK,
1642};
1643static const unsigned int vin5_clk_pins[] = {
1644 RCAR_GP_PIN(9, 0),
1645};
1646static const unsigned int vin5_clk_mux[] = {
1647 VI5_CLK_MARK,
1648};
1649
1650static const struct sh_pfc_pin_group pinmux_groups[] = {
1651 SH_PFC_PIN_GROUP(avb_link),
1652 SH_PFC_PIN_GROUP(avb_magic),
1653 SH_PFC_PIN_GROUP(avb_phy_int),
1654 SH_PFC_PIN_GROUP(avb_mdio),
1655 SH_PFC_PIN_GROUP(avb_mii),
1656 SH_PFC_PIN_GROUP(avb_gmii),
1657 SH_PFC_PIN_GROUP(avb_avtp_match),
1658 SH_PFC_PIN_GROUP(can0_data),
1659 SH_PFC_PIN_GROUP(can1_data),
1660 SH_PFC_PIN_GROUP(can_clk),
1661 SH_PFC_PIN_GROUP(du0_rgb666),
1662 SH_PFC_PIN_GROUP(du0_rgb888),
1663 SH_PFC_PIN_GROUP(du0_sync),
1664 SH_PFC_PIN_GROUP(du0_oddf),
1665 SH_PFC_PIN_GROUP(du0_disp),
1666 SH_PFC_PIN_GROUP(du0_cde),
1667 SH_PFC_PIN_GROUP(du1_rgb666),
1668 SH_PFC_PIN_GROUP(du1_sync),
1669 SH_PFC_PIN_GROUP(du1_oddf),
1670 SH_PFC_PIN_GROUP(du1_disp),
1671 SH_PFC_PIN_GROUP(du1_cde),
1672 SH_PFC_PIN_GROUP(intc_irq0),
1673 SH_PFC_PIN_GROUP(intc_irq1),
1674 SH_PFC_PIN_GROUP(intc_irq2),
1675 SH_PFC_PIN_GROUP(intc_irq3),
1676 SH_PFC_PIN_GROUP(lbsc_cs0),
1677 SH_PFC_PIN_GROUP(lbsc_cs1),
1678 SH_PFC_PIN_GROUP(lbsc_ex_cs0),
1679 SH_PFC_PIN_GROUP(lbsc_ex_cs1),
1680 SH_PFC_PIN_GROUP(lbsc_ex_cs2),
1681 SH_PFC_PIN_GROUP(lbsc_ex_cs3),
1682 SH_PFC_PIN_GROUP(lbsc_ex_cs4),
1683 SH_PFC_PIN_GROUP(lbsc_ex_cs5),
1684 SH_PFC_PIN_GROUP(msiof0_clk),
1685 SH_PFC_PIN_GROUP(msiof0_sync),
1686 SH_PFC_PIN_GROUP(msiof0_rx),
1687 SH_PFC_PIN_GROUP(msiof0_tx),
1688 SH_PFC_PIN_GROUP(msiof1_clk),
1689 SH_PFC_PIN_GROUP(msiof1_sync),
1690 SH_PFC_PIN_GROUP(msiof1_rx),
1691 SH_PFC_PIN_GROUP(msiof1_tx),
1692 SH_PFC_PIN_GROUP(qspi_ctrl),
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1693 BUS_DATA_PIN_GROUP(qspi_data, 2),
1694 BUS_DATA_PIN_GROUP(qspi_data, 4),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1695 SH_PFC_PIN_GROUP(scif0_data),
1696 SH_PFC_PIN_GROUP(scif0_clk),
1697 SH_PFC_PIN_GROUP(scif0_ctrl),
1698 SH_PFC_PIN_GROUP(scif1_data),
1699 SH_PFC_PIN_GROUP(scif1_clk),
1700 SH_PFC_PIN_GROUP(scif1_ctrl),
1701 SH_PFC_PIN_GROUP(scif2_data),
1702 SH_PFC_PIN_GROUP(scif2_clk),
1703 SH_PFC_PIN_GROUP(scif3_data),
1704 SH_PFC_PIN_GROUP(scif3_clk),
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1705 BUS_DATA_PIN_GROUP(sdhi0_data, 1),
1706 BUS_DATA_PIN_GROUP(sdhi0_data, 4),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1707 SH_PFC_PIN_GROUP(sdhi0_ctrl),
1708 SH_PFC_PIN_GROUP(sdhi0_cd),
1709 SH_PFC_PIN_GROUP(sdhi0_wp),
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1710 BUS_DATA_PIN_GROUP(vin0_data, 24),
1711 BUS_DATA_PIN_GROUP(vin0_data, 20),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1712 SH_PFC_PIN_GROUP(vin0_data18),
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1713 BUS_DATA_PIN_GROUP(vin0_data, 16),
1714 BUS_DATA_PIN_GROUP(vin0_data, 12),
1715 BUS_DATA_PIN_GROUP(vin0_data, 10),
1716 BUS_DATA_PIN_GROUP(vin0_data, 8),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1717 SH_PFC_PIN_GROUP(vin0_sync),
1718 SH_PFC_PIN_GROUP(vin0_field),
1719 SH_PFC_PIN_GROUP(vin0_clkenb),
1720 SH_PFC_PIN_GROUP(vin0_clk),
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1721 BUS_DATA_PIN_GROUP(vin1_data, 24),
1722 BUS_DATA_PIN_GROUP(vin1_data, 20),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1723 SH_PFC_PIN_GROUP(vin1_data18),
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1724 BUS_DATA_PIN_GROUP(vin1_data, 16),
1725 BUS_DATA_PIN_GROUP(vin1_data, 12),
1726 BUS_DATA_PIN_GROUP(vin1_data, 10),
1727 BUS_DATA_PIN_GROUP(vin1_data, 8),
1728 BUS_DATA_PIN_GROUP(vin1_data, 24, _b),
1729 BUS_DATA_PIN_GROUP(vin1_data, 20, _b),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1730 SH_PFC_PIN_GROUP(vin1_data18_b),
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1731 BUS_DATA_PIN_GROUP(vin1_data, 16, _b),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1732 SH_PFC_PIN_GROUP(vin1_sync),
1733 SH_PFC_PIN_GROUP(vin1_field),
1734 SH_PFC_PIN_GROUP(vin1_clkenb),
1735 SH_PFC_PIN_GROUP(vin1_clk),
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1736 BUS_DATA_PIN_GROUP(vin2_data, 16),
1737 BUS_DATA_PIN_GROUP(vin2_data, 12),
1738 BUS_DATA_PIN_GROUP(vin2_data, 10),
1739 BUS_DATA_PIN_GROUP(vin2_data, 8),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1740 SH_PFC_PIN_GROUP(vin2_sync),
1741 SH_PFC_PIN_GROUP(vin2_field),
1742 SH_PFC_PIN_GROUP(vin2_clkenb),
1743 SH_PFC_PIN_GROUP(vin2_clk),
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1744 BUS_DATA_PIN_GROUP(vin3_data, 16),
1745 BUS_DATA_PIN_GROUP(vin3_data, 12),
1746 BUS_DATA_PIN_GROUP(vin3_data, 10),
1747 BUS_DATA_PIN_GROUP(vin3_data, 8),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1748 SH_PFC_PIN_GROUP(vin3_sync),
1749 SH_PFC_PIN_GROUP(vin3_field),
1750 SH_PFC_PIN_GROUP(vin3_clkenb),
1751 SH_PFC_PIN_GROUP(vin3_clk),
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1752 BUS_DATA_PIN_GROUP(vin4_data, 12),
1753 BUS_DATA_PIN_GROUP(vin4_data, 10),
1754 BUS_DATA_PIN_GROUP(vin4_data, 8),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1755 SH_PFC_PIN_GROUP(vin4_sync),
1756 SH_PFC_PIN_GROUP(vin4_field),
1757 SH_PFC_PIN_GROUP(vin4_clkenb),
1758 SH_PFC_PIN_GROUP(vin4_clk),
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1759 BUS_DATA_PIN_GROUP(vin5_data, 12),
1760 BUS_DATA_PIN_GROUP(vin5_data, 10),
1761 BUS_DATA_PIN_GROUP(vin5_data, 8),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1762 SH_PFC_PIN_GROUP(vin5_sync),
1763 SH_PFC_PIN_GROUP(vin5_field),
1764 SH_PFC_PIN_GROUP(vin5_clkenb),
1765 SH_PFC_PIN_GROUP(vin5_clk),
1766};
1767
1768static const char * const avb_groups[] = {
1769 "avb_link",
1770 "avb_magic",
1771 "avb_phy_int",
1772 "avb_mdio",
1773 "avb_mii",
1774 "avb_gmii",
1775 "avb_avtp_match",
1776};
1777
1778static const char * const can0_groups[] = {
1779 "can0_data",
1780 "can_clk",
1781};
1782
1783static const char * const can1_groups[] = {
1784 "can1_data",
1785 "can_clk",
1786};
1787
1788static const char * const du0_groups[] = {
1789 "du0_rgb666",
1790 "du0_rgb888",
1791 "du0_sync",
1792 "du0_oddf",
1793 "du0_disp",
1794 "du0_cde",
1795};
1796
1797static const char * const du1_groups[] = {
1798 "du1_rgb666",
1799 "du1_sync",
1800 "du1_oddf",
1801 "du1_disp",
1802 "du1_cde",
1803};
1804
1805static const char * const intc_groups[] = {
1806 "intc_irq0",
1807 "intc_irq1",
1808 "intc_irq2",
1809 "intc_irq3",
1810};
1811
1812static const char * const lbsc_groups[] = {
1813 "lbsc_cs0",
1814 "lbsc_cs1",
1815 "lbsc_ex_cs0",
1816 "lbsc_ex_cs1",
1817 "lbsc_ex_cs2",
1818 "lbsc_ex_cs3",
1819 "lbsc_ex_cs4",
1820 "lbsc_ex_cs5",
1821};
1822
1823static const char * const msiof0_groups[] = {
1824 "msiof0_clk",
1825 "msiof0_sync",
1826 "msiof0_rx",
1827 "msiof0_tx",
1828};
1829
1830static const char * const msiof1_groups[] = {
1831 "msiof1_clk",
1832 "msiof1_sync",
1833 "msiof1_rx",
1834 "msiof1_tx",
1835};
1836
1837static const char * const qspi_groups[] = {
1838 "qspi_ctrl",
1839 "qspi_data2",
1840 "qspi_data4",
1841};
1842
1843static const char * const scif0_groups[] = {
1844 "scif0_data",
1845 "scif0_clk",
1846 "scif0_ctrl",
1847};
1848
1849static const char * const scif1_groups[] = {
1850 "scif1_data",
1851 "scif1_clk",
1852 "scif1_ctrl",
1853};
1854
1855static const char * const scif2_groups[] = {
1856 "scif2_data",
1857 "scif2_clk",
1858};
1859
1860static const char * const scif3_groups[] = {
1861 "scif3_data",
1862 "scif3_clk",
1863};
1864
1865static const char * const sdhi0_groups[] = {
1866 "sdhi0_data1",
1867 "sdhi0_data4",
1868 "sdhi0_ctrl",
1869 "sdhi0_cd",
1870 "sdhi0_wp",
1871};
1872
1873static const char * const vin0_groups[] = {
1874 "vin0_data24",
1875 "vin0_data20",
1876 "vin0_data18",
1877 "vin0_data16",
1878 "vin0_data12",
1879 "vin0_data10",
1880 "vin0_data8",
1881 "vin0_sync",
1882 "vin0_field",
1883 "vin0_clkenb",
1884 "vin0_clk",
1885};
1886
1887static const char * const vin1_groups[] = {
1888 "vin1_data24",
1889 "vin1_data20",
1890 "vin1_data18",
1891 "vin1_data16",
1892 "vin1_data12",
1893 "vin1_data10",
1894 "vin1_data8",
1895 "vin1_data24_b",
1896 "vin1_data20_b",
Marek Vasut0913c7a2019-03-04 22:26:28 +0100[diff] [blame]1897 "vin1_data18_b",
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1898 "vin1_data16_b",
1899 "vin1_sync",
1900 "vin1_field",
1901 "vin1_clkenb",
1902 "vin1_clk",
1903};
1904
1905static const char * const vin2_groups[] = {
1906 "vin2_data16",
1907 "vin2_data12",
1908 "vin2_data10",
1909 "vin2_data8",
1910 "vin2_sync",
1911 "vin2_field",
1912 "vin2_clkenb",
1913 "vin2_clk",
1914};
1915
1916static const char * const vin3_groups[] = {
1917 "vin3_data16",
1918 "vin3_data12",
1919 "vin3_data10",
1920 "vin3_data8",
1921 "vin3_sync",
1922 "vin3_field",
1923 "vin3_clkenb",
1924 "vin3_clk",
1925};
1926
1927static const char * const vin4_groups[] = {
1928 "vin4_data12",
1929 "vin4_data10",
1930 "vin4_data8",
1931 "vin4_sync",
1932 "vin4_field",
1933 "vin4_clkenb",
1934 "vin4_clk",
1935};
1936
1937static const char * const vin5_groups[] = {
1938 "vin5_data12",
1939 "vin5_data10",
1940 "vin5_data8",
1941 "vin5_sync",
1942 "vin5_field",
1943 "vin5_clkenb",
1944 "vin5_clk",
1945};
1946
1947static const struct sh_pfc_function pinmux_functions[] = {
1948 SH_PFC_FUNCTION(avb),
1949 SH_PFC_FUNCTION(can0),
1950 SH_PFC_FUNCTION(can1),
1951 SH_PFC_FUNCTION(du0),
1952 SH_PFC_FUNCTION(du1),
1953 SH_PFC_FUNCTION(intc),
1954 SH_PFC_FUNCTION(lbsc),
1955 SH_PFC_FUNCTION(msiof0),
1956 SH_PFC_FUNCTION(msiof1),
1957 SH_PFC_FUNCTION(qspi),
1958 SH_PFC_FUNCTION(scif0),
1959 SH_PFC_FUNCTION(scif1),
1960 SH_PFC_FUNCTION(scif2),
1961 SH_PFC_FUNCTION(scif3),
1962 SH_PFC_FUNCTION(sdhi0),
1963 SH_PFC_FUNCTION(vin0),
1964 SH_PFC_FUNCTION(vin1),
1965 SH_PFC_FUNCTION(vin2),
1966 SH_PFC_FUNCTION(vin3),
1967 SH_PFC_FUNCTION(vin4),
1968 SH_PFC_FUNCTION(vin5),
1969};
1970
1971static const struct pinmux_cfg_reg pinmux_config_regs[] = {
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1972 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1973 0, 0,
1974 0, 0,
1975 0, 0,
1976 GP_0_28_FN, FN_IP1_4,
1977 GP_0_27_FN, FN_IP1_3,
1978 GP_0_26_FN, FN_IP1_2,
1979 GP_0_25_FN, FN_IP1_1,
1980 GP_0_24_FN, FN_IP1_0,
1981 GP_0_23_FN, FN_IP0_23,
1982 GP_0_22_FN, FN_IP0_22,
1983 GP_0_21_FN, FN_IP0_21,
1984 GP_0_20_FN, FN_IP0_20,
1985 GP_0_19_FN, FN_IP0_19,
1986 GP_0_18_FN, FN_IP0_18,
1987 GP_0_17_FN, FN_IP0_17,
1988 GP_0_16_FN, FN_IP0_16,
1989 GP_0_15_FN, FN_IP0_15,
1990 GP_0_14_FN, FN_IP0_14,
1991 GP_0_13_FN, FN_IP0_13,
1992 GP_0_12_FN, FN_IP0_12,
1993 GP_0_11_FN, FN_IP0_11,
1994 GP_0_10_FN, FN_IP0_10,
1995 GP_0_9_FN, FN_IP0_9,
1996 GP_0_8_FN, FN_IP0_8,
1997 GP_0_7_FN, FN_IP0_7,
1998 GP_0_6_FN, FN_IP0_6,
1999 GP_0_5_FN, FN_IP0_5,
2000 GP_0_4_FN, FN_IP0_4,
2001 GP_0_3_FN, FN_IP0_3,
2002 GP_0_2_FN, FN_IP0_2,
2003 GP_0_1_FN, FN_IP0_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2004 GP_0_0_FN, FN_IP0_0 ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2005 },
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2006 { PINMUX_CFG_REG_VAR("GPSR1", 0xE6060008, 32,
2007 GROUP(-9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2008 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
2009 GROUP(
2010 /* GP1_31_23 RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2011 GP_1_22_FN, FN_DU1_CDE,
2012 GP_1_21_FN, FN_DU1_DISP,
2013 GP_1_20_FN, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
2014 GP_1_19_FN, FN_DU1_EXVSYNC_DU1_VSYNC,
2015 GP_1_18_FN, FN_DU1_EXHSYNC_DU1_HSYNC,
2016 GP_1_17_FN, FN_DU1_DB7_C5,
2017 GP_1_16_FN, FN_DU1_DB6_C4,
2018 GP_1_15_FN, FN_DU1_DB5_C3_DATA15,
2019 GP_1_14_FN, FN_DU1_DB4_C2_DATA14,
2020 GP_1_13_FN, FN_DU1_DB3_C1_DATA13,
2021 GP_1_12_FN, FN_DU1_DB2_C0_DATA12,
2022 GP_1_11_FN, FN_IP1_16,
2023 GP_1_10_FN, FN_IP1_15,
2024 GP_1_9_FN, FN_IP1_14,
2025 GP_1_8_FN, FN_IP1_13,
2026 GP_1_7_FN, FN_IP1_12,
2027 GP_1_6_FN, FN_IP1_11,
2028 GP_1_5_FN, FN_IP1_10,
2029 GP_1_4_FN, FN_IP1_9,
2030 GP_1_3_FN, FN_IP1_8,
2031 GP_1_2_FN, FN_IP1_7,
2032 GP_1_1_FN, FN_IP1_6,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2033 GP_1_0_FN, FN_IP1_5, ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2034 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2035 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2036 GP_2_31_FN, FN_A15,
2037 GP_2_30_FN, FN_A14,
2038 GP_2_29_FN, FN_A13,
2039 GP_2_28_FN, FN_A12,
2040 GP_2_27_FN, FN_A11,
2041 GP_2_26_FN, FN_A10,
2042 GP_2_25_FN, FN_A9,
2043 GP_2_24_FN, FN_A8,
2044 GP_2_23_FN, FN_A7,
2045 GP_2_22_FN, FN_A6,
2046 GP_2_21_FN, FN_A5,
2047 GP_2_20_FN, FN_A4,
2048 GP_2_19_FN, FN_A3,
2049 GP_2_18_FN, FN_A2,
2050 GP_2_17_FN, FN_A1,
2051 GP_2_16_FN, FN_A0,
2052 GP_2_15_FN, FN_D15,
2053 GP_2_14_FN, FN_D14,
2054 GP_2_13_FN, FN_D13,
2055 GP_2_12_FN, FN_D12,
2056 GP_2_11_FN, FN_D11,
2057 GP_2_10_FN, FN_D10,
2058 GP_2_9_FN, FN_D9,
2059 GP_2_8_FN, FN_D8,
2060 GP_2_7_FN, FN_D7,
2061 GP_2_6_FN, FN_D6,
2062 GP_2_5_FN, FN_D5,
2063 GP_2_4_FN, FN_D4,
2064 GP_2_3_FN, FN_D3,
2065 GP_2_2_FN, FN_D2,
2066 GP_2_1_FN, FN_D1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2067 GP_2_0_FN, FN_D0 ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2068 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2069 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2070 0, 0,
2071 0, 0,
2072 0, 0,
2073 0, 0,
2074 GP_3_27_FN, FN_CS0_N,
2075 GP_3_26_FN, FN_IP1_22,
2076 GP_3_25_FN, FN_IP1_21,
2077 GP_3_24_FN, FN_IP1_20,
2078 GP_3_23_FN, FN_IP1_19,
2079 GP_3_22_FN, FN_IRQ3,
2080 GP_3_21_FN, FN_IRQ2,
2081 GP_3_20_FN, FN_IRQ1,
2082 GP_3_19_FN, FN_IRQ0,
2083 GP_3_18_FN, FN_EX_WAIT0,
2084 GP_3_17_FN, FN_WE1_N,
2085 GP_3_16_FN, FN_WE0_N,
2086 GP_3_15_FN, FN_RD_WR_N,
2087 GP_3_14_FN, FN_RD_N,
2088 GP_3_13_FN, FN_BS_N,
2089 GP_3_12_FN, FN_EX_CS5_N,
2090 GP_3_11_FN, FN_EX_CS4_N,
2091 GP_3_10_FN, FN_EX_CS3_N,
2092 GP_3_9_FN, FN_EX_CS2_N,
2093 GP_3_8_FN, FN_EX_CS1_N,
2094 GP_3_7_FN, FN_EX_CS0_N,
2095 GP_3_6_FN, FN_CS1_N_A26,
2096 GP_3_5_FN, FN_IP1_18,
2097 GP_3_4_FN, FN_IP1_17,
2098 GP_3_3_FN, FN_A19,
2099 GP_3_2_FN, FN_A18,
2100 GP_3_1_FN, FN_A17,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2101 GP_3_0_FN, FN_A16 ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2102 },
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2103 { PINMUX_CFG_REG_VAR("GPSR4", 0xE6060014, 32,
2104 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2105 1, 1, 1, 1, 1, 1),
2106 GROUP(
2107 /* GP4_31_17 RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2108 GP_4_16_FN, FN_VI0_FIELD,
2109 GP_4_15_FN, FN_VI0_D11_G3_Y3,
2110 GP_4_14_FN, FN_VI0_D10_G2_Y2,
2111 GP_4_13_FN, FN_VI0_D9_G1_Y1,
2112 GP_4_12_FN, FN_VI0_D8_G0_Y0,
2113 GP_4_11_FN, FN_VI0_D7_B7_C7,
2114 GP_4_10_FN, FN_VI0_D6_B6_C6,
2115 GP_4_9_FN, FN_VI0_D5_B5_C5,
2116 GP_4_8_FN, FN_VI0_D4_B4_C4,
2117 GP_4_7_FN, FN_VI0_D3_B3_C3,
2118 GP_4_6_FN, FN_VI0_D2_B2_C2,
2119 GP_4_5_FN, FN_VI0_D1_B1_C1,
2120 GP_4_4_FN, FN_VI0_D0_B0_C0,
2121 GP_4_3_FN, FN_VI0_VSYNC_N,
2122 GP_4_2_FN, FN_VI0_HSYNC_N,
2123 GP_4_1_FN, FN_VI0_CLKENB,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2124 GP_4_0_FN, FN_VI0_CLK ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2125 },
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2126 { PINMUX_CFG_REG_VAR("GPSR5", 0xE6060018, 32,
2127 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2128 1, 1, 1, 1, 1, 1),
2129 GROUP(
2130 /* GP5_31_17 RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2131 GP_5_16_FN, FN_VI1_FIELD,
2132 GP_5_15_FN, FN_VI1_D11_G3_Y3,
2133 GP_5_14_FN, FN_VI1_D10_G2_Y2,
2134 GP_5_13_FN, FN_VI1_D9_G1_Y1,
2135 GP_5_12_FN, FN_VI1_D8_G0_Y0,
2136 GP_5_11_FN, FN_VI1_D7_B7_C7,
2137 GP_5_10_FN, FN_VI1_D6_B6_C6,
2138 GP_5_9_FN, FN_VI1_D5_B5_C5,
2139 GP_5_8_FN, FN_VI1_D4_B4_C4,
2140 GP_5_7_FN, FN_VI1_D3_B3_C3,
2141 GP_5_6_FN, FN_VI1_D2_B2_C2,
2142 GP_5_5_FN, FN_VI1_D1_B1_C1,
2143 GP_5_4_FN, FN_VI1_D0_B0_C0,
2144 GP_5_3_FN, FN_VI1_VSYNC_N,
2145 GP_5_2_FN, FN_VI1_HSYNC_N,
2146 GP_5_1_FN, FN_VI1_CLKENB,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2147 GP_5_0_FN, FN_VI1_CLK ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2148 },
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2149 { PINMUX_CFG_REG_VAR("GPSR6", 0xE606001C, 32,
2150 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2151 1, 1, 1, 1, 1, 1),
2152 GROUP(
2153 /* GP6_31_17 RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2154 GP_6_16_FN, FN_IP2_16,
2155 GP_6_15_FN, FN_IP2_15,
2156 GP_6_14_FN, FN_IP2_14,
2157 GP_6_13_FN, FN_IP2_13,
2158 GP_6_12_FN, FN_IP2_12,
2159 GP_6_11_FN, FN_IP2_11,
2160 GP_6_10_FN, FN_IP2_10,
2161 GP_6_9_FN, FN_IP2_9,
2162 GP_6_8_FN, FN_IP2_8,
2163 GP_6_7_FN, FN_IP2_7,
2164 GP_6_6_FN, FN_IP2_6,
2165 GP_6_5_FN, FN_IP2_5,
2166 GP_6_4_FN, FN_IP2_4,
2167 GP_6_3_FN, FN_IP2_3,
2168 GP_6_2_FN, FN_IP2_2,
2169 GP_6_1_FN, FN_IP2_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2170 GP_6_0_FN, FN_IP2_0 ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2171 },
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2172 { PINMUX_CFG_REG_VAR("GPSR7", 0xE6060020, 32,
2173 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2174 1, 1, 1, 1, 1, 1),
2175 GROUP(
2176 /* GP7_31_17 RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2177 GP_7_16_FN, FN_VI3_FIELD,
2178 GP_7_15_FN, FN_IP3_14,
2179 GP_7_14_FN, FN_VI3_D10_Y2,
2180 GP_7_13_FN, FN_IP3_13,
2181 GP_7_12_FN, FN_IP3_12,
2182 GP_7_11_FN, FN_IP3_11,
2183 GP_7_10_FN, FN_IP3_10,
2184 GP_7_9_FN, FN_IP3_9,
2185 GP_7_8_FN, FN_IP3_8,
2186 GP_7_7_FN, FN_IP3_7,
2187 GP_7_6_FN, FN_IP3_6,
2188 GP_7_5_FN, FN_IP3_5,
2189 GP_7_4_FN, FN_IP3_4,
2190 GP_7_3_FN, FN_IP3_3,
2191 GP_7_2_FN, FN_IP3_2,
2192 GP_7_1_FN, FN_IP3_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2193 GP_7_0_FN, FN_IP3_0 ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2194 },
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2195 { PINMUX_CFG_REG_VAR("GPSR8", 0xE6060024, 32,
2196 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2197 1, 1, 1, 1, 1, 1),
2198 GROUP(
2199 /* GP8_31_17 RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2200 GP_8_16_FN, FN_IP4_24,
2201 GP_8_15_FN, FN_IP4_23,
2202 GP_8_14_FN, FN_IP4_22,
2203 GP_8_13_FN, FN_IP4_21,
2204 GP_8_12_FN, FN_IP4_20_19,
2205 GP_8_11_FN, FN_IP4_18_17,
2206 GP_8_10_FN, FN_IP4_16_15,
2207 GP_8_9_FN, FN_IP4_14_13,
2208 GP_8_8_FN, FN_IP4_12_11,
2209 GP_8_7_FN, FN_IP4_10_9,
2210 GP_8_6_FN, FN_IP4_8_7,
2211 GP_8_5_FN, FN_IP4_6_5,
2212 GP_8_4_FN, FN_IP4_4,
2213 GP_8_3_FN, FN_IP4_3_2,
2214 GP_8_2_FN, FN_IP4_1,
2215 GP_8_1_FN, FN_IP4_0,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2216 GP_8_0_FN, FN_VI4_CLK ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2217 },
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2218 { PINMUX_CFG_REG_VAR("GPSR9", 0xE6060028, 32,
2219 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2220 1, 1, 1, 1, 1, 1),
2221 GROUP(
2222 /* GP9_31_17 RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2223 GP_9_16_FN, FN_VI5_FIELD,
2224 GP_9_15_FN, FN_VI5_D11_Y3,
2225 GP_9_14_FN, FN_VI5_D10_Y2,
2226 GP_9_13_FN, FN_VI5_D9_Y1,
2227 GP_9_12_FN, FN_IP5_11,
2228 GP_9_11_FN, FN_IP5_10,
2229 GP_9_10_FN, FN_IP5_9,
2230 GP_9_9_FN, FN_IP5_8,
2231 GP_9_8_FN, FN_IP5_7,
2232 GP_9_7_FN, FN_IP5_6,
2233 GP_9_6_FN, FN_IP5_5,
2234 GP_9_5_FN, FN_IP5_4,
2235 GP_9_4_FN, FN_IP5_3,
2236 GP_9_3_FN, FN_IP5_2,
2237 GP_9_2_FN, FN_IP5_1,
2238 GP_9_1_FN, FN_IP5_0,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2239 GP_9_0_FN, FN_VI5_CLK ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2240 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2241 { PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1, GROUP(
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2242 GP_10_31_FN, FN_CAN1_RX,
2243 GP_10_30_FN, FN_CAN1_TX,
2244 GP_10_29_FN, FN_CAN_CLK,
2245 GP_10_28_FN, FN_CAN0_RX,
2246 GP_10_27_FN, FN_CAN0_TX,
2247 GP_10_26_FN, FN_SCIF_CLK,
2248 GP_10_25_FN, FN_IP6_18_17,
2249 GP_10_24_FN, FN_IP6_16,
2250 GP_10_23_FN, FN_IP6_15_14,
2251 GP_10_22_FN, FN_IP6_13_12,
2252 GP_10_21_FN, FN_IP6_11_10,
2253 GP_10_20_FN, FN_IP6_9_8,
2254 GP_10_19_FN, FN_RX1,
2255 GP_10_18_FN, FN_TX1,
2256 GP_10_17_FN, FN_RTS1_N,
2257 GP_10_16_FN, FN_CTS1_N,
2258 GP_10_15_FN, FN_SCK1,
2259 GP_10_14_FN, FN_RX0,
2260 GP_10_13_FN, FN_TX0,
2261 GP_10_12_FN, FN_RTS0_N,
2262 GP_10_11_FN, FN_CTS0_N,
2263 GP_10_10_FN, FN_SCK0,
2264 GP_10_9_FN, FN_IP6_7,
2265 GP_10_8_FN, FN_IP6_6,
2266 GP_10_7_FN, FN_HCTS1_N,
2267 GP_10_6_FN, FN_IP6_5,
2268 GP_10_5_FN, FN_IP6_4,
2269 GP_10_4_FN, FN_IP6_3,
2270 GP_10_3_FN, FN_IP6_2,
2271 GP_10_2_FN, FN_HRTS0_N,
2272 GP_10_1_FN, FN_IP6_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2273 GP_10_0_FN, FN_IP6_0 ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2274 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2275 { PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1, GROUP(
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2276 0, 0,
2277 0, 0,
2278 GP_11_29_FN, FN_AVS2,
2279 GP_11_28_FN, FN_AVS1,
2280 GP_11_27_FN, FN_ADICHS2,
2281 GP_11_26_FN, FN_ADICHS1,
2282 GP_11_25_FN, FN_ADICHS0,
2283 GP_11_24_FN, FN_ADIDATA,
2284 GP_11_23_FN, FN_ADICS_SAMP,
2285 GP_11_22_FN, FN_ADICLK,
2286 GP_11_21_FN, FN_IP7_20,
2287 GP_11_20_FN, FN_IP7_19,
2288 GP_11_19_FN, FN_IP7_18,
2289 GP_11_18_FN, FN_IP7_17,
2290 GP_11_17_FN, FN_IP7_16,
2291 GP_11_16_FN, FN_IP7_15_14,
2292 GP_11_15_FN, FN_IP7_13_12,
2293 GP_11_14_FN, FN_IP7_11_10,
2294 GP_11_13_FN, FN_IP7_9_8,
2295 GP_11_12_FN, FN_SD0_WP,
2296 GP_11_11_FN, FN_SD0_CD,
2297 GP_11_10_FN, FN_SD0_DAT3,
2298 GP_11_9_FN, FN_SD0_DAT2,
2299 GP_11_8_FN, FN_SD0_DAT1,
2300 GP_11_7_FN, FN_SD0_DAT0,
2301 GP_11_6_FN, FN_SD0_CMD,
2302 GP_11_5_FN, FN_SD0_CLK,
2303 GP_11_4_FN, FN_IP7_7,
2304 GP_11_3_FN, FN_IP7_6,
2305 GP_11_2_FN, FN_IP7_5_4,
2306 GP_11_1_FN, FN_IP7_3_2,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2307 GP_11_0_FN, FN_IP7_1_0 ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2308 },
2309 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2310 GROUP(-8,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2311 1, 1, 1, 1, 1, 1, 1, 1,
2312 1, 1, 1, 1, 1, 1, 1, 1,
2313 1, 1, 1, 1, 1, 1, 1, 1),
2314 GROUP(
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2315 /* IP0_31_24 [8] RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2316 /* IP0_23 [1] */
2317 FN_DU0_DB7_C5, 0,
2318 /* IP0_22 [1] */
2319 FN_DU0_DB6_C4, 0,
2320 /* IP0_21 [1] */
2321 FN_DU0_DB5_C3, 0,
2322 /* IP0_20 [1] */
2323 FN_DU0_DB4_C2, 0,
2324 /* IP0_19 [1] */
2325 FN_DU0_DB3_C1, 0,
2326 /* IP0_18 [1] */
2327 FN_DU0_DB2_C0, 0,
2328 /* IP0_17 [1] */
2329 FN_DU0_DB1, 0,
2330 /* IP0_16 [1] */
2331 FN_DU0_DB0, 0,
2332 /* IP0_15 [1] */
2333 FN_DU0_DG7_Y3_DATA15, 0,
2334 /* IP0_14 [1] */
2335 FN_DU0_DG6_Y2_DATA14, 0,
2336 /* IP0_13 [1] */
2337 FN_DU0_DG5_Y1_DATA13, 0,
2338 /* IP0_12 [1] */
2339 FN_DU0_DG4_Y0_DATA12, 0,
2340 /* IP0_11 [1] */
2341 FN_DU0_DG3_C7_DATA11, 0,
2342 /* IP0_10 [1] */
2343 FN_DU0_DG2_C6_DATA10, 0,
2344 /* IP0_9 [1] */
2345 FN_DU0_DG1_DATA9, 0,
2346 /* IP0_8 [1] */
2347 FN_DU0_DG0_DATA8, 0,
2348 /* IP0_7 [1] */
2349 FN_DU0_DR7_Y9_DATA7, 0,
2350 /* IP0_6 [1] */
2351 FN_DU0_DR6_Y8_DATA6, 0,
2352 /* IP0_5 [1] */
2353 FN_DU0_DR5_Y7_DATA5, 0,
2354 /* IP0_4 [1] */
2355 FN_DU0_DR4_Y6_DATA4, 0,
2356 /* IP0_3 [1] */
2357 FN_DU0_DR3_Y5_DATA3, 0,
2358 /* IP0_2 [1] */
2359 FN_DU0_DR2_Y4_DATA2, 0,
2360 /* IP0_1 [1] */
2361 FN_DU0_DR1_DATA1, 0,
2362 /* IP0_0 [1] */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2363 FN_DU0_DR0_DATA0, 0 ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2364 },
2365 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2366 GROUP(-9, 1, 1, 1, 1, 1, 1, 1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2367 1, 1, 1, 1, 1, 1, 1, 1,
2368 1, 1, 1, 1, 1, 1, 1, 1),
2369 GROUP(
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2370 /* IP1_31_23 [9] RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2371 /* IP1_22 [1] */
2372 FN_A25, FN_SSL,
2373 /* IP1_21 [1] */
2374 FN_A24, FN_SPCLK,
2375 /* IP1_20 [1] */
2376 FN_A23, FN_IO3,
2377 /* IP1_19 [1] */
2378 FN_A22, FN_IO2,
2379 /* IP1_18 [1] */
2380 FN_A21, FN_MISO_IO1,
2381 /* IP1_17 [1] */
2382 FN_A20, FN_MOSI_IO0,
2383 /* IP1_16 [1] */
2384 FN_DU1_DG7_Y3_DATA11, 0,
2385 /* IP1_15 [1] */
2386 FN_DU1_DG6_Y2_DATA10, 0,
2387 /* IP1_14 [1] */
2388 FN_DU1_DG5_Y1_DATA9, 0,
2389 /* IP1_13 [1] */
2390 FN_DU1_DG4_Y0_DATA8, 0,
2391 /* IP1_12 [1] */
2392 FN_DU1_DG3_C7_DATA7, 0,
2393 /* IP1_11 [1] */
2394 FN_DU1_DG2_C6_DATA6, 0,
2395 /* IP1_10 [1] */
2396 FN_DU1_DR7_DATA5, 0,
2397 /* IP1_9 [1] */
2398 FN_DU1_DR6_DATA4, 0,
2399 /* IP1_8 [1] */
2400 FN_DU1_DR5_Y7_DATA3, 0,
2401 /* IP1_7 [1] */
2402 FN_DU1_DR4_Y6_DATA2, 0,
2403 /* IP1_6 [1] */
2404 FN_DU1_DR3_Y5_DATA1, 0,
2405 /* IP1_5 [1] */
2406 FN_DU1_DR2_Y4_DATA0, 0,
2407 /* IP1_4 [1] */
2408 FN_DU0_CDE, 0,
2409 /* IP1_3 [1] */
2410 FN_DU0_DISP, 0,
2411 /* IP1_2 [1] */
2412 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, 0,
2413 /* IP1_1 [1] */
2414 FN_DU0_EXVSYNC_DU0_VSYNC, 0,
2415 /* IP1_0 [1] */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2416 FN_DU0_EXHSYNC_DU0_HSYNC, 0 ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2417 },
2418 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2419 GROUP(-15, 1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2420 1, 1, 1, 1, 1, 1, 1, 1,
2421 1, 1, 1, 1, 1, 1, 1, 1),
2422 GROUP(
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2423 /* IP2_31_17 [15] RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2424 /* IP2_16 [1] */
2425 FN_VI2_FIELD, FN_AVB_TXD2,
2426 /* IP2_15 [1] */
2427 FN_VI2_D11_Y3, FN_AVB_TXD1,
2428 /* IP2_14 [1] */
2429 FN_VI2_D10_Y2, FN_AVB_TXD0,
2430 /* IP2_13 [1] */
2431 FN_VI2_D9_Y1, FN_AVB_TX_EN,
2432 /* IP2_12 [1] */
2433 FN_VI2_D8_Y0, FN_AVB_TXD3,
2434 /* IP2_11 [1] */
2435 FN_VI2_D7_C7, FN_AVB_COL,
2436 /* IP2_10 [1] */
2437 FN_VI2_D6_C6, FN_AVB_RX_ER,
2438 /* IP2_9 [1] */
2439 FN_VI2_D5_C5, FN_AVB_RXD7,
2440 /* IP2_8 [1] */
2441 FN_VI2_D4_C4, FN_AVB_RXD6,
2442 /* IP2_7 [1] */
2443 FN_VI2_D3_C3, FN_AVB_RXD5,
2444 /* IP2_6 [1] */
2445 FN_VI2_D2_C2, FN_AVB_RXD4,
2446 /* IP2_5 [1] */
2447 FN_VI2_D1_C1, FN_AVB_RXD3,
2448 /* IP2_4 [1] */
2449 FN_VI2_D0_C0, FN_AVB_RXD2,
2450 /* IP2_3 [1] */
2451 FN_VI2_VSYNC_N, FN_AVB_RXD1,
2452 /* IP2_2 [1] */
2453 FN_VI2_HSYNC_N, FN_AVB_RXD0,
2454 /* IP2_1 [1] */
2455 FN_VI2_CLKENB, FN_AVB_RX_DV,
2456 /* IP2_0 [1] */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2457 FN_VI2_CLK, FN_AVB_RX_CLK ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2458 },
2459 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2460 GROUP(-17, 1, 1, 1, 1, 1, 1, 1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2461 1, 1, 1, 1, 1, 1, 1, 1),
2462 GROUP(
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2463 /* IP3_31_15 [17] RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2464 /* IP3_14 [1] */
2465 FN_VI3_D11_Y3, FN_AVB_AVTP_MATCH,
2466 /* IP3_13 [1] */
2467 FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,
2468 /* IP3_12 [1] */
2469 FN_VI3_D8_Y0, FN_AVB_CRS,
2470 /* IP3_11 [1] */
2471 FN_VI3_D7_C7, FN_AVB_PHY_INT,
2472 /* IP3_10 [1] */
2473 FN_VI3_D6_C6, FN_AVB_MAGIC,
2474 /* IP3_9 [1] */
2475 FN_VI3_D5_C5, FN_AVB_LINK,
2476 /* IP3_8 [1] */
2477 FN_VI3_D4_C4, FN_AVB_MDIO,
2478 /* IP3_7 [1] */
2479 FN_VI3_D3_C3, FN_AVB_MDC,
2480 /* IP3_6 [1] */
2481 FN_VI3_D2_C2, FN_AVB_GTX_CLK,
2482 /* IP3_5 [1] */
2483 FN_VI3_D1_C1, FN_AVB_TX_ER,
2484 /* IP3_4 [1] */
2485 FN_VI3_D0_C0, FN_AVB_TXD7,
2486 /* IP3_3 [1] */
2487 FN_VI3_VSYNC_N, FN_AVB_TXD6,
2488 /* IP3_2 [1] */
2489 FN_VI3_HSYNC_N, FN_AVB_TXD5,
2490 /* IP3_1 [1] */
2491 FN_VI3_CLKENB, FN_AVB_TXD4,
2492 /* IP3_0 [1] */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2493 FN_VI3_CLK, FN_AVB_TX_CLK ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2494 },
2495 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2496 GROUP(-7, 1, 1, 1, 1, 2, 2, 2,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2497 2, 2, 2, 2, 2, 1, 2, 1, 1),
2498 GROUP(
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2499 /* IP4_31_25 [7] RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2500 /* IP4_24 [1] */
2501 FN_VI4_FIELD, FN_VI3_D15_Y7,
2502 /* IP4_23 [1] */
2503 FN_VI4_D11_Y3, FN_VI3_D14_Y6,
2504 /* IP4_22 [1] */
2505 FN_VI4_D10_Y2, FN_VI3_D13_Y5,
2506 /* IP4_21 [1] */
2507 FN_VI4_D9_Y1, FN_VI3_D12_Y4,
2508 /* IP4_20_19 [2] */
2509 FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7, 0,
2510 /* IP4_18_17 [2] */
2511 FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6, 0,
2512 /* IP4_16_15 [2] */
2513 FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5, 0,
2514 /* IP4_14_13 [2] */
2515 FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4, 0,
2516 /* IP4_12_11 [2] */
2517 FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7, 0,
2518 /* IP4_10_9 [2] */
2519 FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6, 0,
2520 /* IP4_8_7 [2] */
2521 FN_VI4_D2_C2, 0, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5,
2522 /* IP4_6_5 [2] */
2523 FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4, 0,
2524 /* IP4_4 [1] */
2525 FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,
2526 /* IP4_3_2 [2] */
2527 FN_VI4_VSYNC_N, FN_VI0_D14_G6_Y6, 0, 0,
2528 /* IP4_1 [1] */
2529 FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5,
2530 /* IP4_0 [1] */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2531 FN_VI4_CLKENB, FN_VI0_D12_G4_Y4 ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2532 },
2533 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2534 GROUP(-20, 1, 1, 1, 1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2535 1, 1, 1, 1, 1, 1, 1, 1),
2536 GROUP(
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2537 /* IP5_31_12 [20] RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2538 /* IP5_11 [1] */
2539 FN_VI5_D8_Y0, FN_VI1_D23_R7,
2540 /* IP5_10 [1] */
2541 FN_VI5_D7_C7, FN_VI1_D22_R6,
2542 /* IP5_9 [1] */
2543 FN_VI5_D6_C6, FN_VI1_D21_R5,
2544 /* IP5_8 [1] */
2545 FN_VI5_D5_C5, FN_VI1_D20_R4,
2546 /* IP5_7 [1] */
2547 FN_VI5_D4_C4, FN_VI1_D19_R3,
2548 /* IP5_6 [1] */
2549 FN_VI5_D3_C3, FN_VI1_D18_R2,
2550 /* IP5_5 [1] */
2551 FN_VI5_D2_C2, FN_VI1_D17_R1,
2552 /* IP5_4 [1] */
2553 FN_VI5_D1_C1, FN_VI1_D16_R0,
2554 /* IP5_3 [1] */
2555 FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_B,
2556 /* IP5_2 [1] */
2557 FN_VI5_VSYNC_N, FN_VI1_D14_G6_Y6_B,
2558 /* IP5_1 [1] */
2559 FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B,
2560 /* IP5_0 [1] */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2561 FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2562 },
2563 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2564 GROUP(-13, 2, 1, 2, 2, 2, 2,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2565 1, 1, 1, 1, 1, 1, 1, 1),
2566 GROUP(
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2567 /* IP6_31_19 [13] RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2568 /* IP6_18_17 [2] */
2569 FN_DREQ1_N, FN_RX3, 0, 0,
2570 /* IP6_16 [1] */
2571 FN_TX3, 0,
2572 /* IP6_15_14 [2] */
2573 FN_DACK1, FN_SCK3, 0, 0,
2574 /* IP6_13_12 [2] */
2575 FN_DREQ0_N, FN_RX2, 0, 0,
2576 /* IP6_11_10 [2] */
2577 FN_DACK0, FN_TX2, 0, 0,
2578 /* IP6_9_8 [2] */
2579 FN_DRACK0, FN_SCK2, 0, 0,
2580 /* IP6_7 [1] */
2581 FN_MSIOF1_RXD, FN_HRX1,
2582 /* IP6_6 [1] */
2583 FN_MSIOF1_TXD, FN_HTX1,
2584 /* IP6_5 [1] */
2585 FN_MSIOF1_SYNC, FN_HRTS1_N,
2586 /* IP6_4 [1] */
2587 FN_MSIOF1_SCK, FN_HSCK1,
2588 /* IP6_3 [1] */
2589 FN_MSIOF0_RXD, FN_HRX0,
2590 /* IP6_2 [1] */
2591 FN_MSIOF0_TXD, FN_HTX0,
2592 /* IP6_1 [1] */
2593 FN_MSIOF0_SYNC, FN_HCTS0_N,
2594 /* IP6_0 [1] */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2595 FN_MSIOF0_SCK, FN_HSCK0 ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2596 },
2597 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2598 GROUP(-11, 1, 1, 1, 1, 1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2599 2, 2, 2, 2,
2600 1, 1, 2, 2, 2),
2601 GROUP(
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2602 /* IP7_31_21 [11] RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2603 /* IP7_20 [1] */
2604 FN_AUDIO_CLKB, 0,
2605 /* IP7_19 [1] */
2606 FN_AUDIO_CLKA, 0,
2607 /* IP7_18 [1] */
2608 FN_AUDIO_CLKOUT, 0,
2609 /* IP7_17 [1] */
2610 FN_SSI_SDATA4, 0,
2611 /* IP7_16 [1] */
2612 FN_SSI_WS4, 0,
2613 /* IP7_15_14 [2] */
2614 FN_SSI_SCK4, FN_TPU0TO3, 0, 0,
2615 /* IP7_13_12 [2] */
2616 FN_SSI_SDATA3, FN_TPU0TO2, 0, 0,
2617 /* IP7_11_10 [2] */
2618 FN_SSI_WS34, FN_TPU0TO1, 0, 0,
2619 /* IP7_9_8 [2] */
2620 FN_SSI_SCK34, FN_TPU0TO0, 0, 0,
2621 /* IP7_7 [1] */
2622 FN_PWM4, 0,
2623 /* IP7_6 [1] */
2624 FN_PWM3, 0,
2625 /* IP7_5_4 [2] */
2626 FN_PWM2, FN_TCLK3, FN_FSO_TOE, 0,
2627 /* IP7_3_2 [2] */
2628 FN_PWM1, FN_TCLK2, FN_FSO_CFE_1, 0,
2629 /* IP7_1_0 [2] */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2630 FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2631 },
2632 { },
2633};
2634
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2635static const struct pinmux_bias_reg pinmux_bias_regs[] = {
2636 { PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) {
2637 [ 0] = RCAR_GP_PIN(0, 0), /* DU0_DR0_DATA0 */
2638 [ 1] = RCAR_GP_PIN(0, 1), /* DU0_DR1_DATA1 */
2639 [ 2] = RCAR_GP_PIN(0, 2), /* DU0_DR2_Y4_DATA2 */
2640 [ 3] = RCAR_GP_PIN(0, 3), /* DU0_DR3_Y5_DATA3 */
2641 [ 4] = RCAR_GP_PIN(0, 4), /* DU0_DR4_Y6_DATA4 */
2642 [ 5] = RCAR_GP_PIN(0, 5), /* DU0_DR5_Y7_DATA5 */
2643 [ 6] = RCAR_GP_PIN(0, 6), /* DU0_DR6_Y8_DATA6 */
2644 [ 7] = RCAR_GP_PIN(0, 7), /* DU0_DR7_Y9_DATA7 */
2645 [ 8] = RCAR_GP_PIN(0, 8), /* DU0_DG0_DATA8 */
2646 [ 9] = RCAR_GP_PIN(0, 9), /* DU0_DG1_DATA9 */
2647 [10] = RCAR_GP_PIN(0, 10), /* DU0_DG2_C6_DATA10 */
2648 [11] = RCAR_GP_PIN(0, 11), /* DU0_DG3_C7_DATA11 */
2649 [12] = RCAR_GP_PIN(0, 12), /* DU0_DG4_Y0_DATA12 */
2650 [13] = RCAR_GP_PIN(0, 13), /* DU0_DG5_Y1_DATA13 */
2651 [14] = RCAR_GP_PIN(0, 14), /* DU0_DG6_Y2_DATA14 */
2652 [15] = RCAR_GP_PIN(0, 15), /* DU0_DG7_Y3_DATA15 */
2653 [16] = RCAR_GP_PIN(0, 16), /* DU0_DB0 */
2654 [17] = RCAR_GP_PIN(0, 17), /* DU0_DB1 */
2655 [18] = RCAR_GP_PIN(0, 18), /* DU0_DB2_C0 */
2656 [19] = RCAR_GP_PIN(0, 19), /* DU0_DB3_C1 */
2657 [20] = RCAR_GP_PIN(0, 20), /* DU0_DB4_C2 */
2658 [21] = RCAR_GP_PIN(0, 21), /* DU0_DB5_C3 */
2659 [22] = RCAR_GP_PIN(0, 22), /* DU0_DB6_C4 */
2660 [23] = RCAR_GP_PIN(0, 23), /* DU0_DB7_C5 */
2661 [24] = RCAR_GP_PIN(0, 24), /* DU0_EXHSYNC/DU0_HSYNC */
2662 [25] = RCAR_GP_PIN(0, 25), /* DU0_EXVSYNC/DU0_VSYNC */
2663 [26] = RCAR_GP_PIN(0, 26), /* DU0_EXODDF/DU0_ODDF_DISP_CDE */
2664 [27] = RCAR_GP_PIN(0, 27), /* DU0_DISP */
2665 [28] = RCAR_GP_PIN(0, 28), /* DU0_CDE */
2666 [29] = SH_PFC_PIN_NONE,
2667 [30] = SH_PFC_PIN_NONE,
2668 [31] = SH_PFC_PIN_NONE,
2669 } },
2670 { PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) {
2671 [ 0] = RCAR_GP_PIN(1, 0), /* DU1_DR2_Y4_DATA0 */
2672 [ 1] = RCAR_GP_PIN(1, 1), /* DU1_DR3_Y5_DATA1 */
2673 [ 2] = RCAR_GP_PIN(1, 2), /* DU1_DR4_Y6_DATA2 */
2674 [ 3] = RCAR_GP_PIN(1, 3), /* DU1_DR5_Y7_DATA3 */
2675 [ 4] = RCAR_GP_PIN(1, 4), /* DU1_DR6_DATA4 */
2676 [ 5] = RCAR_GP_PIN(1, 5), /* DU1_DR7_DATA5 */
2677 [ 6] = RCAR_GP_PIN(1, 6), /* DU1_DG2_C6_DATA6 */
2678 [ 7] = RCAR_GP_PIN(1, 7), /* DU1_DG3_C7_DATA7 */
2679 [ 8] = RCAR_GP_PIN(1, 8), /* DU1_DG4_Y0_DATA8 */
2680 [ 9] = RCAR_GP_PIN(1, 9), /* DU1_DG5_Y1_DATA9 */
2681 [10] = RCAR_GP_PIN(1, 10), /* DU1_DG6_Y2_DATA10 */
2682 [11] = RCAR_GP_PIN(1, 11), /* DU1_DG7_Y3_DATA11 */
2683 [12] = RCAR_GP_PIN(1, 12), /* DU1_DB2_C0_DATA12 */
2684 [13] = RCAR_GP_PIN(1, 13), /* DU1_DB3_C1_DATA13 */
2685 [14] = RCAR_GP_PIN(1, 14), /* DU1_DB4_C2_DATA14 */
2686 [15] = RCAR_GP_PIN(1, 15), /* DU1_DB5_C3_DATA15 */
2687 [16] = RCAR_GP_PIN(1, 16), /* DU1_DB6_C4 */
2688 [17] = RCAR_GP_PIN(1, 17), /* DU1_DB7_C5 */
2689 [18] = RCAR_GP_PIN(1, 18), /* DU1_EXHSYNC/DU1_HSYNC */
2690 [19] = RCAR_GP_PIN(1, 19), /* DU1_EXVSYNC/DU1_VSYNC */
2691 [20] = RCAR_GP_PIN(1, 20), /* DU1_EXODDF/DU1_ODDF_DISP_CDE */
2692 [21] = RCAR_GP_PIN(1, 21), /* DU1_DISP */
2693 [22] = RCAR_GP_PIN(1, 22), /* DU1_CDE */
2694 [23] = SH_PFC_PIN_NONE,
2695 [24] = SH_PFC_PIN_NONE,
2696 [25] = SH_PFC_PIN_NONE,
2697 [26] = SH_PFC_PIN_NONE,
2698 [27] = SH_PFC_PIN_NONE,
2699 [28] = SH_PFC_PIN_NONE,
2700 [29] = SH_PFC_PIN_NONE,
2701 [30] = SH_PFC_PIN_NONE,
2702 [31] = SH_PFC_PIN_NONE,
2703 } },
2704 { PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) {
2705 [ 0] = RCAR_GP_PIN(2, 0), /* D0 */
2706 [ 1] = RCAR_GP_PIN(2, 1), /* D1 */
2707 [ 2] = RCAR_GP_PIN(2, 2), /* D2 */
2708 [ 3] = RCAR_GP_PIN(2, 3), /* D3 */
2709 [ 4] = RCAR_GP_PIN(2, 4), /* D4 */
2710 [ 5] = RCAR_GP_PIN(2, 5), /* D5 */
2711 [ 6] = RCAR_GP_PIN(2, 6), /* D6 */
2712 [ 7] = RCAR_GP_PIN(2, 7), /* D7 */
2713 [ 8] = RCAR_GP_PIN(2, 8), /* D8 */
2714 [ 9] = RCAR_GP_PIN(2, 9), /* D9 */
2715 [10] = RCAR_GP_PIN(2, 10), /* D10 */
2716 [11] = RCAR_GP_PIN(2, 11), /* D11 */
2717 [12] = RCAR_GP_PIN(2, 12), /* D12 */
2718 [13] = RCAR_GP_PIN(2, 13), /* D13 */
2719 [14] = RCAR_GP_PIN(2, 14), /* D14 */
2720 [15] = RCAR_GP_PIN(2, 15), /* D15 */
2721 [16] = RCAR_GP_PIN(2, 16), /* A0 */
2722 [17] = RCAR_GP_PIN(2, 17), /* A1 */
2723 [18] = RCAR_GP_PIN(2, 18), /* A2 */
2724 [19] = RCAR_GP_PIN(2, 19), /* A3 */
2725 [20] = RCAR_GP_PIN(2, 20), /* A4 */
2726 [21] = RCAR_GP_PIN(2, 21), /* A5 */
2727 [22] = RCAR_GP_PIN(2, 22), /* A6 */
2728 [23] = RCAR_GP_PIN(2, 23), /* A7 */
2729 [24] = RCAR_GP_PIN(2, 24), /* A8 */
2730 [25] = RCAR_GP_PIN(2, 25), /* A9 */
2731 [26] = RCAR_GP_PIN(2, 26), /* A10 */
2732 [27] = RCAR_GP_PIN(2, 27), /* A11 */
2733 [28] = RCAR_GP_PIN(2, 28), /* A12 */
2734 [29] = RCAR_GP_PIN(2, 29), /* A13 */
2735 [30] = RCAR_GP_PIN(2, 30), /* A14 */
2736 [31] = RCAR_GP_PIN(2, 31), /* A15 */
2737 } },
2738 { PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) {
2739 [ 0] = RCAR_GP_PIN(3, 0), /* A16 */
2740 [ 1] = RCAR_GP_PIN(3, 1), /* A17 */
2741 [ 2] = RCAR_GP_PIN(3, 2), /* A18 */
2742 [ 3] = RCAR_GP_PIN(3, 3), /* A19 */
2743 [ 4] = RCAR_GP_PIN(3, 4), /* A20 */
2744 [ 5] = RCAR_GP_PIN(3, 5), /* A21 */
2745 [ 6] = RCAR_GP_PIN(3, 6), /* CS1#/A26 */
2746 [ 7] = RCAR_GP_PIN(3, 7), /* EX_CS0# */
2747 [ 8] = RCAR_GP_PIN(3, 8), /* EX_CS1# */
2748 [ 9] = RCAR_GP_PIN(3, 9), /* EX_CS2# */
2749 [10] = RCAR_GP_PIN(3, 10), /* EX_CS3# */
2750 [11] = RCAR_GP_PIN(3, 11), /* EX_CS4# */
2751 [12] = RCAR_GP_PIN(3, 12), /* EX_CS5# */
2752 [13] = RCAR_GP_PIN(3, 13), /* BS# */
2753 [14] = RCAR_GP_PIN(3, 14), /* RD# */
2754 [15] = RCAR_GP_PIN(3, 15), /* RD/WR# */
2755 [16] = RCAR_GP_PIN(3, 16), /* WE0# */
2756 [17] = RCAR_GP_PIN(3, 17), /* WE1# */
2757 [18] = RCAR_GP_PIN(3, 18), /* EX_WAIT0 */
2758 [19] = RCAR_GP_PIN(3, 19), /* IRQ0 */
2759 [20] = RCAR_GP_PIN(3, 20), /* IRQ1 */
2760 [21] = RCAR_GP_PIN(3, 21), /* IRQ2 */
2761 [22] = RCAR_GP_PIN(3, 22), /* IRQ3 */
2762 [23] = RCAR_GP_PIN(3, 23), /* A22 */
2763 [24] = RCAR_GP_PIN(3, 24), /* A23 */
2764 [25] = RCAR_GP_PIN(3, 25), /* A24 */
2765 [26] = RCAR_GP_PIN(3, 26), /* A25 */
2766 [27] = RCAR_GP_PIN(3, 27), /* CS0# */
2767 [28] = SH_PFC_PIN_NONE,
2768 [29] = SH_PFC_PIN_NONE,
2769 [30] = SH_PFC_PIN_NONE,
2770 [31] = SH_PFC_PIN_NONE,
2771 } },
2772 { PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) {
2773 [ 0] = RCAR_GP_PIN(4, 0), /* VI0_CLK */
2774 [ 1] = RCAR_GP_PIN(4, 1), /* VI0_CLKENB */
2775 [ 2] = RCAR_GP_PIN(4, 2), /* VI0_HSYNC# */
2776 [ 3] = RCAR_GP_PIN(4, 3), /* VI0_VSYNC# */
2777 [ 4] = RCAR_GP_PIN(4, 4), /* VI0_D0_B0_C0 */
2778 [ 5] = RCAR_GP_PIN(4, 5), /* VI0_D1_B1_C1 */
2779 [ 6] = RCAR_GP_PIN(4, 6), /* VI0_D2_B2_C2 */
2780 [ 7] = RCAR_GP_PIN(4, 7), /* VI0_D3_B3_C3 */
2781 [ 8] = RCAR_GP_PIN(4, 8), /* VI0_D4_B4_C4 */
2782 [ 9] = RCAR_GP_PIN(4, 9), /* VI0_D5_B5_C5 */
2783 [10] = RCAR_GP_PIN(4, 10), /* VI0_D6_B6_C6 */
2784 [11] = RCAR_GP_PIN(4, 11), /* VI0_D7_B7_C7 */
2785 [12] = RCAR_GP_PIN(4, 12), /* VI0_D8_G0_Y0 */
2786 [13] = RCAR_GP_PIN(4, 13), /* VI0_D9_G1_Y1 */
2787 [14] = RCAR_GP_PIN(4, 14), /* VI0_D10_G2_Y2 */
2788 [15] = RCAR_GP_PIN(4, 15), /* VI0_D11_G3_Y3 */
2789 [16] = RCAR_GP_PIN(4, 16), /* VI0_FIELD */
2790 [17] = SH_PFC_PIN_NONE,
2791 [18] = SH_PFC_PIN_NONE,
2792 [19] = SH_PFC_PIN_NONE,
2793 [20] = SH_PFC_PIN_NONE,
2794 [21] = SH_PFC_PIN_NONE,
2795 [22] = SH_PFC_PIN_NONE,
2796 [23] = SH_PFC_PIN_NONE,
2797 [24] = SH_PFC_PIN_NONE,
2798 [25] = SH_PFC_PIN_NONE,
2799 [26] = SH_PFC_PIN_NONE,
2800 [27] = SH_PFC_PIN_NONE,
2801 [28] = SH_PFC_PIN_NONE,
2802 [29] = SH_PFC_PIN_NONE,
2803 [30] = SH_PFC_PIN_NONE,
2804 [31] = SH_PFC_PIN_NONE,
2805 } },
2806 { PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) {
2807 [ 0] = RCAR_GP_PIN(5, 0), /* VI1_CLK */
2808 [ 1] = RCAR_GP_PIN(5, 1), /* VI1_CLKENB */
2809 [ 2] = RCAR_GP_PIN(5, 2), /* VI1_HSYNC# */
2810 [ 3] = RCAR_GP_PIN(5, 3), /* VI1_VSYNC# */
2811 [ 4] = RCAR_GP_PIN(5, 4), /* VI1_D0_B0_C0 */
2812 [ 5] = RCAR_GP_PIN(5, 5), /* VI1_D1_B1_C1 */
2813 [ 6] = RCAR_GP_PIN(5, 6), /* VI1_D2_B2_C2 */
2814 [ 7] = RCAR_GP_PIN(5, 7), /* VI1_D3_B3_C3 */
2815 [ 8] = RCAR_GP_PIN(5, 8), /* VI1_D4_B4_C4 */
2816 [ 9] = RCAR_GP_PIN(5, 9), /* VI1_D5_B5_C5 */
2817 [10] = RCAR_GP_PIN(5, 10), /* VI1_D6_B6_C6 */
2818 [11] = RCAR_GP_PIN(5, 11), /* VI1_D7_B7_C7 */
2819 [12] = RCAR_GP_PIN(5, 12), /* VI1_D8_G0_Y0 */
2820 [13] = RCAR_GP_PIN(5, 13), /* VI1_D9_G1_Y1 */
2821 [14] = RCAR_GP_PIN(5, 14), /* VI1_D10_G2_Y2 */
2822 [15] = RCAR_GP_PIN(5, 15), /* VI1_D11_G3_Y3 */
2823 [16] = RCAR_GP_PIN(5, 16), /* VI1_FIELD */
2824 [17] = SH_PFC_PIN_NONE,
2825 [18] = SH_PFC_PIN_NONE,
2826 [19] = SH_PFC_PIN_NONE,
2827 [20] = SH_PFC_PIN_NONE,
2828 [21] = SH_PFC_PIN_NONE,
2829 [22] = SH_PFC_PIN_NONE,
2830 [23] = SH_PFC_PIN_NONE,
2831 [24] = SH_PFC_PIN_NONE,
2832 [25] = SH_PFC_PIN_NONE,
2833 [26] = SH_PFC_PIN_NONE,
2834 [27] = SH_PFC_PIN_NONE,
2835 [28] = SH_PFC_PIN_NONE,
2836 [29] = SH_PFC_PIN_NONE,
2837 [30] = SH_PFC_PIN_NONE,
2838 [31] = SH_PFC_PIN_NONE,
2839 } },
2840 { PINMUX_BIAS_REG("PUPR6", 0xe6060118, "N/A", 0) {
2841 [ 0] = RCAR_GP_PIN(6, 0), /* VI2_CLK */
2842 [ 1] = RCAR_GP_PIN(6, 1), /* VI2_CLKENB */
2843 [ 2] = RCAR_GP_PIN(6, 2), /* VI2_HSYNC# */
2844 [ 3] = RCAR_GP_PIN(6, 3), /* VI2_VSYNC# */
2845 [ 4] = RCAR_GP_PIN(6, 4), /* VI2_D0_C0 */
2846 [ 5] = RCAR_GP_PIN(6, 5), /* VI2_D1_C1 */
2847 [ 6] = RCAR_GP_PIN(6, 6), /* VI2_D2_C2 */
2848 [ 7] = RCAR_GP_PIN(6, 7), /* VI2_D3_C3 */
2849 [ 8] = RCAR_GP_PIN(6, 8), /* VI2_D4_C4 */
2850 [ 9] = RCAR_GP_PIN(6, 9), /* VI2_D5_C5 */
2851 [10] = RCAR_GP_PIN(6, 10), /* VI2_D6_C6 */
2852 [11] = RCAR_GP_PIN(6, 11), /* VI2_D7_C7 */
2853 [12] = RCAR_GP_PIN(6, 12), /* VI2_D8_Y0 */
2854 [13] = RCAR_GP_PIN(6, 13), /* VI2_D9_Y1 */
2855 [14] = RCAR_GP_PIN(6, 14), /* VI2_D10_Y2 */
2856 [15] = RCAR_GP_PIN(6, 15), /* VI2_D11_Y3 */
2857 [16] = RCAR_GP_PIN(6, 16), /* VI2_FIELD */
2858 [17] = SH_PFC_PIN_NONE,
2859 [18] = SH_PFC_PIN_NONE,
2860 [19] = SH_PFC_PIN_NONE,
2861 [20] = SH_PFC_PIN_NONE,
2862 [21] = SH_PFC_PIN_NONE,
2863 [22] = SH_PFC_PIN_NONE,
2864 [23] = SH_PFC_PIN_NONE,
2865 [24] = SH_PFC_PIN_NONE,
2866 [25] = SH_PFC_PIN_NONE,
2867 [26] = SH_PFC_PIN_NONE,
2868 [27] = SH_PFC_PIN_NONE,
2869 [28] = SH_PFC_PIN_NONE,
2870 [29] = SH_PFC_PIN_NONE,
2871 [30] = SH_PFC_PIN_NONE,
2872 [31] = SH_PFC_PIN_NONE,
2873 } },
2874 { PINMUX_BIAS_REG("PUPR7", 0xe606011c, "N/A", 0) {
2875 [ 0] = RCAR_GP_PIN(7, 0), /* VI3_CLK */
2876 [ 1] = RCAR_GP_PIN(7, 1), /* VI3_CLKENB */
2877 [ 2] = RCAR_GP_PIN(7, 2), /* VI3_HSYNC# */
2878 [ 3] = RCAR_GP_PIN(7, 3), /* VI3_VSYNC# */
2879 [ 4] = RCAR_GP_PIN(7, 4), /* VI3_D0_C0 */
2880 [ 5] = RCAR_GP_PIN(7, 5), /* VI3_D1_C1 */
2881 [ 6] = RCAR_GP_PIN(7, 6), /* VI3_D2_C2 */
2882 [ 7] = RCAR_GP_PIN(7, 7), /* VI3_D3_C3 */
2883 [ 8] = RCAR_GP_PIN(7, 8), /* VI3_D4_C4 */
2884 [ 9] = RCAR_GP_PIN(7, 9), /* VI3_D5_C5 */
2885 [10] = RCAR_GP_PIN(7, 10), /* VI3_D6_C6 */
2886 [11] = RCAR_GP_PIN(7, 11), /* VI3_D7_C7 */
2887 [12] = RCAR_GP_PIN(7, 12), /* VI3_D8_Y0 */
2888 [13] = RCAR_GP_PIN(7, 13), /* VI3_D9_Y1 */
2889 [14] = RCAR_GP_PIN(7, 14), /* VI3_D10_Y2 */
2890 [15] = RCAR_GP_PIN(7, 15), /* VI3_D11_Y3 */
2891 [16] = RCAR_GP_PIN(7, 16), /* VI3_FIELD */
2892 [17] = SH_PFC_PIN_NONE,
2893 [18] = SH_PFC_PIN_NONE,
2894 [19] = SH_PFC_PIN_NONE,
2895 [20] = SH_PFC_PIN_NONE,
2896 [21] = SH_PFC_PIN_NONE,
2897 [22] = SH_PFC_PIN_NONE,
2898 [23] = SH_PFC_PIN_NONE,
2899 [24] = SH_PFC_PIN_NONE,
2900 [25] = SH_PFC_PIN_NONE,
2901 [26] = SH_PFC_PIN_NONE,
2902 [27] = SH_PFC_PIN_NONE,
2903 [28] = SH_PFC_PIN_NONE,
2904 [29] = SH_PFC_PIN_NONE,
2905 [30] = SH_PFC_PIN_NONE,
2906 [31] = SH_PFC_PIN_NONE,
2907 } },
2908 { PINMUX_BIAS_REG("PUPR8", 0xe6060120, "N/A", 0) {
2909 [ 0] = RCAR_GP_PIN(8, 0), /* VI4_CLK */
2910 [ 1] = RCAR_GP_PIN(8, 1), /* VI4_CLKENB */
2911 [ 2] = RCAR_GP_PIN(8, 2), /* VI4_HSYNC# */
2912 [ 3] = RCAR_GP_PIN(8, 3), /* VI4_VSYNC# */
2913 [ 4] = RCAR_GP_PIN(8, 4), /* VI4_D0_C0 */
2914 [ 5] = RCAR_GP_PIN(8, 5), /* VI4_D1_C1 */
2915 [ 6] = RCAR_GP_PIN(8, 6), /* VI4_D2_C2 */
2916 [ 7] = RCAR_GP_PIN(8, 7), /* VI4_D3_C3 */
2917 [ 8] = RCAR_GP_PIN(8, 8), /* VI4_D4_C4 */
2918 [ 9] = RCAR_GP_PIN(8, 9), /* VI4_D5_C5 */
2919 [10] = RCAR_GP_PIN(8, 10), /* VI4_D6_C6 */
2920 [11] = RCAR_GP_PIN(8, 11), /* VI4_D7_C7 */
2921 [12] = RCAR_GP_PIN(8, 12), /* VI4_D8_Y0 */
2922 [13] = RCAR_GP_PIN(8, 13), /* VI4_D9_Y1 */
2923 [14] = RCAR_GP_PIN(8, 14), /* VI4_D10_Y2 */
2924 [15] = RCAR_GP_PIN(8, 15), /* VI4_D11_Y3 */
2925 [16] = RCAR_GP_PIN(8, 16), /* VI4_FIELD */
2926 [17] = SH_PFC_PIN_NONE,
2927 [18] = SH_PFC_PIN_NONE,
2928 [19] = SH_PFC_PIN_NONE,
2929 [20] = SH_PFC_PIN_NONE,
2930 [21] = SH_PFC_PIN_NONE,
2931 [22] = SH_PFC_PIN_NONE,
2932 [23] = SH_PFC_PIN_NONE,
2933 [24] = SH_PFC_PIN_NONE,
2934 [25] = SH_PFC_PIN_NONE,
2935 [26] = SH_PFC_PIN_NONE,
2936 [27] = SH_PFC_PIN_NONE,
2937 [28] = SH_PFC_PIN_NONE,
2938 [29] = SH_PFC_PIN_NONE,
2939 [30] = SH_PFC_PIN_NONE,
2940 [31] = SH_PFC_PIN_NONE,
2941 } },
2942 { PINMUX_BIAS_REG("PUPR9", 0xe6060124, "N/A", 0) {
2943 [ 0] = RCAR_GP_PIN(9, 0), /* VI5_CLK */
2944 [ 1] = RCAR_GP_PIN(9, 1), /* VI5_CLKENB */
2945 [ 2] = RCAR_GP_PIN(9, 2), /* VI5_HSYNC# */
2946 [ 3] = RCAR_GP_PIN(9, 3), /* VI5_VSYNC# */
2947 [ 4] = RCAR_GP_PIN(9, 4), /* VI5_D0_C0 */
2948 [ 5] = RCAR_GP_PIN(9, 5), /* VI5_D1_C1 */
2949 [ 6] = RCAR_GP_PIN(9, 6), /* VI5_D2_C2 */
2950 [ 7] = RCAR_GP_PIN(9, 7), /* VI5_D3_C3 */
2951 [ 8] = RCAR_GP_PIN(9, 8), /* VI5_D4_C4 */
2952 [ 9] = RCAR_GP_PIN(9, 9), /* VI5_D5_C5 */
2953 [10] = RCAR_GP_PIN(9, 10), /* VI5_D6_C6 */
2954 [11] = RCAR_GP_PIN(9, 11), /* VI5_D7_C7 */
2955 [12] = RCAR_GP_PIN(9, 12), /* VI5_D8_Y0 */
2956 [13] = RCAR_GP_PIN(9, 13), /* VI5_D9_Y1 */
2957 [14] = RCAR_GP_PIN(9, 14), /* VI5_D10_Y2 */
2958 [15] = RCAR_GP_PIN(9, 15), /* VI5_D11_Y3 */
2959 [16] = RCAR_GP_PIN(9, 16), /* VI5_FIELD */
2960 [17] = SH_PFC_PIN_NONE,
2961 [18] = SH_PFC_PIN_NONE,
2962 [19] = SH_PFC_PIN_NONE,
2963 [20] = SH_PFC_PIN_NONE,
2964 [21] = SH_PFC_PIN_NONE,
2965 [22] = SH_PFC_PIN_NONE,
2966 [23] = SH_PFC_PIN_NONE,
2967 [24] = SH_PFC_PIN_NONE,
2968 [25] = SH_PFC_PIN_NONE,
2969 [26] = SH_PFC_PIN_NONE,
2970 [27] = SH_PFC_PIN_NONE,
2971 [28] = SH_PFC_PIN_NONE,
2972 [29] = SH_PFC_PIN_NONE,
2973 [30] = SH_PFC_PIN_NONE,
2974 [31] = SH_PFC_PIN_NONE,
2975 } },
2976 { PINMUX_BIAS_REG("PUPR10", 0xe6060128, "N/A", 0) {
2977 [ 0] = RCAR_GP_PIN(10, 0), /* HSCK0 */
2978 [ 1] = RCAR_GP_PIN(10, 1), /* HCTS0# */
2979 [ 2] = RCAR_GP_PIN(10, 2), /* HRTS0# */
2980 [ 3] = RCAR_GP_PIN(10, 3), /* HTX0 */
2981 [ 4] = RCAR_GP_PIN(10, 4), /* HRX0 */
2982 [ 5] = RCAR_GP_PIN(10, 5), /* HSCK1 */
2983 [ 6] = RCAR_GP_PIN(10, 6), /* HRTS1# */
2984 [ 7] = RCAR_GP_PIN(10, 7), /* HCTS1# */
2985 [ 8] = RCAR_GP_PIN(10, 8), /* HTX1 */
2986 [ 9] = RCAR_GP_PIN(10, 9), /* HRX1 */
2987 [10] = RCAR_GP_PIN(10, 10), /* SCK0 */
2988 [11] = RCAR_GP_PIN(10, 11), /* CTS0# */
2989 [12] = RCAR_GP_PIN(10, 12), /* RTS0# */
2990 [13] = RCAR_GP_PIN(10, 13), /* TX0 */
2991 [14] = RCAR_GP_PIN(10, 14), /* RX0 */
2992 [15] = RCAR_GP_PIN(10, 15), /* SCK1 */
2993 [16] = RCAR_GP_PIN(10, 16), /* CTS1# */
2994 [17] = RCAR_GP_PIN(10, 17), /* RTS1# */
2995 [18] = RCAR_GP_PIN(10, 18), /* TX1 */
2996 [19] = RCAR_GP_PIN(10, 19), /* RX1 */
2997 [20] = RCAR_GP_PIN(10, 20), /* SCK2 */
2998 [21] = RCAR_GP_PIN(10, 21), /* TX2 */
2999 [22] = RCAR_GP_PIN(10, 22), /* RX2 */
3000 [23] = RCAR_GP_PIN(10, 23), /* SCK3 */
3001 [24] = RCAR_GP_PIN(10, 24), /* TX3 */
3002 [25] = RCAR_GP_PIN(10, 25), /* RX3 */
3003 [26] = RCAR_GP_PIN(10, 26), /* SCIF_CLK */
3004 [27] = RCAR_GP_PIN(10, 27), /* CAN0_TX */
3005 [28] = RCAR_GP_PIN(10, 28), /* CAN0_RX */
3006 [29] = RCAR_GP_PIN(10, 29), /* CAN_CLK */
3007 [30] = RCAR_GP_PIN(10, 30), /* CAN1_TX */
3008 [31] = RCAR_GP_PIN(10, 31), /* CAN1_RX */
3009 } },
3010 { PINMUX_BIAS_REG("PUPR11", 0xe606012c, "N/A", 0) {
3011 [ 0] = RCAR_GP_PIN(11, 0), /* PWM0 */
3012 [ 1] = RCAR_GP_PIN(11, 1), /* PWM1 */
3013 [ 2] = RCAR_GP_PIN(11, 2), /* PWM2 */
3014 [ 3] = RCAR_GP_PIN(11, 3), /* PWM3 */
3015 [ 4] = RCAR_GP_PIN(11, 4), /* PWM4 */
3016 [ 5] = RCAR_GP_PIN(11, 5), /* SD0_CLK */
3017 [ 6] = RCAR_GP_PIN(11, 6), /* SD0_CMD */
3018 [ 7] = RCAR_GP_PIN(11, 7), /* SD0_DAT0 */
3019 [ 8] = RCAR_GP_PIN(11, 8), /* SD0_DAT1 */
3020 [ 9] = RCAR_GP_PIN(11, 9), /* SD0_DAT2 */
3021 [10] = RCAR_GP_PIN(11, 10), /* SD0_DAT3 */
3022 [11] = RCAR_GP_PIN(11, 11), /* SD0_CD */
3023 [12] = RCAR_GP_PIN(11, 12), /* SD0_WP */
3024 [13] = RCAR_GP_PIN(11, 13), /* SSI_SCK3 */
3025 [14] = RCAR_GP_PIN(11, 14), /* SSI_WS3 */
3026 [15] = RCAR_GP_PIN(11, 15), /* SSI_SDATA3 */
3027 [16] = RCAR_GP_PIN(11, 16), /* SSI_SCK4 */
3028 [17] = RCAR_GP_PIN(11, 17), /* SSI_WS4 */
3029 [18] = RCAR_GP_PIN(11, 18), /* SSI_SDATA4 */
3030 [19] = RCAR_GP_PIN(11, 19), /* AUDIO_CLKOUT */
3031 [20] = RCAR_GP_PIN(11, 20), /* AUDIO_CLKA */
3032 [21] = RCAR_GP_PIN(11, 21), /* AUDIO_CLKB */
3033 [22] = RCAR_GP_PIN(11, 22), /* ADICLK */
3034 [23] = RCAR_GP_PIN(11, 23), /* ADICS_SAMP */
3035 [24] = RCAR_GP_PIN(11, 24), /* ADIDATA */
3036 [25] = RCAR_GP_PIN(11, 25), /* ADICHS0 */
3037 [26] = RCAR_GP_PIN(11, 26), /* ADICHS1 */
3038 [27] = RCAR_GP_PIN(11, 27), /* ADICHS2 */
3039 [28] = RCAR_GP_PIN(11, 28), /* AVS1 */
3040 [29] = RCAR_GP_PIN(11, 29), /* AVS2 */
3041 [30] = SH_PFC_PIN_NONE,
3042 [31] = SH_PFC_PIN_NONE,
3043 } },
3044 { PINMUX_BIAS_REG("PUPR12", 0xe6060130, "N/A", 0) {
3045 /* PUPR12 pull-up pins */
3046 [ 0] = PIN_DU0_DOTCLKIN, /* DU0_DOTCLKIN */
3047 [ 1] = PIN_DU0_DOTCLKOUT, /* DU0_DOTCLKOUT */
3048 [ 2] = PIN_DU1_DOTCLKIN, /* DU1_DOTCLKIN */
3049 [ 3] = PIN_DU1_DOTCLKOUT, /* DU1_DOTCLKOUT */
3050 [ 4] = PIN_TRST_N, /* TRST# */
3051 [ 5] = PIN_TCK, /* TCK */
3052 [ 6] = PIN_TMS, /* TMS */
3053 [ 7] = PIN_TDI, /* TDI */
3054 [ 8] = SH_PFC_PIN_NONE,
3055 [ 9] = SH_PFC_PIN_NONE,
3056 [10] = SH_PFC_PIN_NONE,
3057 [11] = SH_PFC_PIN_NONE,
3058 [12] = SH_PFC_PIN_NONE,
3059 [13] = SH_PFC_PIN_NONE,
3060 [14] = SH_PFC_PIN_NONE,
3061 [15] = SH_PFC_PIN_NONE,
3062 [16] = SH_PFC_PIN_NONE,
3063 [17] = SH_PFC_PIN_NONE,
3064 [18] = SH_PFC_PIN_NONE,
3065 [19] = SH_PFC_PIN_NONE,
3066 [20] = SH_PFC_PIN_NONE,
3067 [21] = SH_PFC_PIN_NONE,
3068 [22] = SH_PFC_PIN_NONE,
3069 [23] = SH_PFC_PIN_NONE,
3070 [24] = SH_PFC_PIN_NONE,
3071 [25] = SH_PFC_PIN_NONE,
3072 [26] = SH_PFC_PIN_NONE,
3073 [27] = SH_PFC_PIN_NONE,
3074 [28] = SH_PFC_PIN_NONE,
3075 [29] = SH_PFC_PIN_NONE,
3076 [30] = SH_PFC_PIN_NONE,
3077 [31] = SH_PFC_PIN_NONE,
3078 } },
3079 { PINMUX_BIAS_REG("N/A", 0, "PUPR12", 0xe6060130) {
3080 /* PUPR12 pull-down pins */
3081 [ 0] = SH_PFC_PIN_NONE,
3082 [ 1] = SH_PFC_PIN_NONE,
3083 [ 2] = SH_PFC_PIN_NONE,
3084 [ 3] = SH_PFC_PIN_NONE,
3085 [ 4] = SH_PFC_PIN_NONE,
3086 [ 5] = SH_PFC_PIN_NONE,
3087 [ 6] = SH_PFC_PIN_NONE,
3088 [ 7] = SH_PFC_PIN_NONE,
3089 [ 8] = PIN_EDBGREQ, /* EDBGREQ */
3090 [ 9] = SH_PFC_PIN_NONE,
3091 [10] = SH_PFC_PIN_NONE,
3092 [11] = SH_PFC_PIN_NONE,
3093 [12] = SH_PFC_PIN_NONE,
3094 [13] = SH_PFC_PIN_NONE,
3095 [14] = SH_PFC_PIN_NONE,
3096 [15] = SH_PFC_PIN_NONE,
3097 [16] = SH_PFC_PIN_NONE,
3098 [17] = SH_PFC_PIN_NONE,
3099 [18] = SH_PFC_PIN_NONE,
3100 [19] = SH_PFC_PIN_NONE,
3101 [20] = SH_PFC_PIN_NONE,
3102 [21] = SH_PFC_PIN_NONE,
3103 [22] = SH_PFC_PIN_NONE,
3104 [23] = SH_PFC_PIN_NONE,
3105 [24] = SH_PFC_PIN_NONE,
3106 [25] = SH_PFC_PIN_NONE,
3107 [26] = SH_PFC_PIN_NONE,
3108 [27] = SH_PFC_PIN_NONE,
3109 [28] = SH_PFC_PIN_NONE,
3110 [29] = SH_PFC_PIN_NONE,
3111 [30] = SH_PFC_PIN_NONE,
3112 [31] = SH_PFC_PIN_NONE,
3113 } },
3114 { /* sentinel */ }
3115};
3116
3117static const struct sh_pfc_soc_operations r8a7792_pfc_ops = {
3118 .get_bias = rcar_pinmux_get_bias,
3119 .set_bias = rcar_pinmux_set_bias,
3120};
3121
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]3122const struct sh_pfc_soc_info r8a7792_pinmux_info = {
3123 .name = "r8a77920_pfc",
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]3124 .ops = &r8a7792_pfc_ops,
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]3125 .unlock_reg = 0xe6060000, /* PMMR */
3126
3127 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3128
3129 .pins = pinmux_pins,
3130 .nr_pins = ARRAY_SIZE(pinmux_pins),
3131 .groups = pinmux_groups,
3132 .nr_groups = ARRAY_SIZE(pinmux_groups),
3133 .functions = pinmux_functions,
3134 .nr_functions = ARRAY_SIZE(pinmux_functions),
3135
3136 .cfg_regs = pinmux_config_regs,
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]3137 .bias_regs = pinmux_bias_regs,
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]3138
3139 .pinmux_data = pinmux_data,
3140 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
3141};