developer | 18ec8d6 | 2020-11-12 16:35:52 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (C) 2020 MediaTek Inc. |
| 4 | * |
| 5 | * Author: Weijie Gao <weijie.gao@mediatek.com> |
| 6 | * |
| 7 | * Definitions of ioctl requests of MT7620 sysc driver |
| 8 | */ |
| 9 | |
| 10 | #ifndef _MT7620_SYSC_H_ |
| 11 | #define _MT7620_SYSC_H_ |
| 12 | |
| 13 | #include <linux/types.h> |
| 14 | |
| 15 | enum mt7620_sysc_requests { |
| 16 | MT7620_SYSC_IOCTL_GET_CLK, |
| 17 | MT7620_SYSC_IOCTL_GET_CHIP_REV, |
| 18 | MT7620_SYSC_IOCTL_SET_GE1_MODE, |
| 19 | MT7620_SYSC_IOCTL_SET_GE2_MODE, |
| 20 | MT7620_SYSC_IOCTL_SET_USB_MODE, |
| 21 | MT7620_SYSC_IOCTL_SET_PCIE_MODE |
| 22 | }; |
| 23 | |
| 24 | struct mt7620_sysc_clks { |
| 25 | u32 cpu_clk; |
| 26 | u32 sys_clk; |
| 27 | u32 xtal_clk; |
| 28 | u32 peri_clk; |
| 29 | }; |
| 30 | |
| 31 | struct mt7620_sysc_chip_rev { |
| 32 | bool bga; |
| 33 | u32 ver : 4; |
| 34 | u32 eco : 4; |
| 35 | }; |
| 36 | |
| 37 | enum mt7620_sysc_ge_mode { |
| 38 | MT7620_SYSC_GE_RGMII, |
| 39 | MT7620_SYSC_GE_MII, |
| 40 | MT7620_SYSC_GE_RMII, |
| 41 | MT7620_SYSC_GE_ESW_PHY, |
| 42 | }; |
| 43 | |
| 44 | enum mt7620_sysc_usb_mode { |
| 45 | MT7620_SYSC_USB_DEVICE_MODE, |
| 46 | MT7620_SYSC_USB_HOST_MODE |
| 47 | }; |
| 48 | |
| 49 | enum mt7620_sysc_pcie_mode { |
| 50 | MT7620_SYSC_PCIE_EP_MODE, |
| 51 | MT7620_SYSC_PCIE_RC_MODE |
| 52 | }; |
| 53 | |
| 54 | #endif /* _MT7620_SYSC_H_ */ |