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git01.mediatek.com / filogic / uboot / 45140f066a9abe616efe58d3d76123dd75dbe790 / . / arch / arm / dts / imx93-11x11-evk-u-boot.dtsi
blob: 5b465e2dbd9d8c4b8bf29cdd433923f286313bad [file] [log] [blame]
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2022 NXP
4 */
5
6/ {
7 wdt-reboot {
8 compatible = "wdt-reboot";
9 wdt = <&wdog3>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]10 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]11 };
12
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]13 firmware {
14 optee {
15 compatible = "linaro,optee-tz";
16 method = "smc";
17 };
18 };
19};
20
21&{/soc@0} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]22 bootph-all;
23 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]24};
25
26&aips1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]27 bootph-pre-ram;
28 bootph-all;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]29};
30
31&aips2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]32 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]33};
34
35&aips3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]36 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]37};
38
39&iomuxc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]40 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]41};
42
43&reg_usdhc2_vmmc {
44 u-boot,off-on-delay-us = <20000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]45 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]46};
47
48&pinctrl_reg_usdhc2_vmmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]49 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]50};
51
52&pinctrl_uart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]53 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]54};
55
56&pinctrl_usdhc2_gpio {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]57 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]58};
59
60&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]61 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]62};
63
64&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]65 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]66};
67
68&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]69 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]70};
71
72&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]73 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]74};
75
76&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]77 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]78};
79
80&lpuart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]81 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]82};
83
84&usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]85 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]86};
87
88&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]89 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]90 fsl,signal-voltage-switch-extra-delay-ms = <8>;
91};
92
93&lpi2c2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]94 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]95};
96
97&{/soc@0/bus@44000000/i2c@44350000/pmic@25} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]98 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]99};
100
101&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]102 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]103};
104
105&pinctrl_lpi2c2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]106 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]107};
108
109&fec {
110 phy-reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
111 phy-reset-duration = <15>;
112 phy-reset-post-delay = <100>;
113};
114
115&eqos {
116 compatible = "fsl,imx-eqos";
117};
118
119&ethphy1 {
120 reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
121 reset-assert-us = <15000>;
122 reset-deassert-us = <100000>;
123};
124
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]125&s4muap {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]126 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]127 status = "okay";
128};