Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Yao Yuan | e0f8f54 | 2015-12-05 14:59:10 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2015 Freescale Semiconductor, Inc. |
Yao Yuan | e0f8f54 | 2015-12-05 14:59:10 +0800 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 7 | #include <log.h> |
Yao Yuan | e0f8f54 | 2015-12-05 14:59:10 +0800 | [diff] [blame] | 8 | #include <asm/arch/clock.h> |
| 9 | #include <asm/io.h> |
Hou Zhiqiang | 4b23ca8 | 2016-08-02 19:03:27 +0800 | [diff] [blame] | 10 | #include <asm/arch/fsl_serdes.h> |
Yao Yuan | e0f8f54 | 2015-12-05 14:59:10 +0800 | [diff] [blame] | 11 | #include <asm/arch/immap_ls102xa.h> |
| 12 | #include <asm/arch/ls102xa_soc.h> |
Alison Wang | 6936492 | 2016-02-05 12:48:17 +0800 | [diff] [blame] | 13 | #include <asm/arch/ls102xa_stream_id.h> |
Hou Zhiqiang | 5ac9a5c | 2016-08-02 19:03:23 +0800 | [diff] [blame] | 14 | #include <fsl_csu.h> |
Tom Rini | 5618460 | 2022-02-25 11:19:53 -0500 | [diff] [blame] | 15 | #ifdef CONFIG_SYS_FSL_ERRATUM_A008850 |
Alison Wang | d6be97b | 2019-03-06 14:49:14 +0800 | [diff] [blame] | 16 | #include <fsl_ddr_sdram.h> |
Tom Rini | 5618460 | 2022-02-25 11:19:53 -0500 | [diff] [blame] | 17 | #endif |
Alison Wang | 6936492 | 2016-02-05 12:48:17 +0800 | [diff] [blame] | 18 | |
| 19 | struct liodn_id_table sec_liodn_tbl[] = { |
| 20 | SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10), |
| 21 | SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10), |
| 22 | SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10), |
| 23 | SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10), |
| 24 | SET_SEC_RTIC_LIODN_ENTRY(a, 0x10), |
| 25 | SET_SEC_RTIC_LIODN_ENTRY(b, 0x10), |
| 26 | SET_SEC_RTIC_LIODN_ENTRY(c, 0x10), |
| 27 | SET_SEC_RTIC_LIODN_ENTRY(d, 0x10), |
| 28 | SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10), |
| 29 | SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10), |
| 30 | SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10), |
| 31 | SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10), |
| 32 | SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10), |
| 33 | SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10), |
| 34 | SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10), |
| 35 | SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10), |
| 36 | }; |
| 37 | |
| 38 | struct smmu_stream_id dev_stream_id[] = { |
| 39 | { 0x100, 0x01, "ETSEC MAC1" }, |
| 40 | { 0x104, 0x02, "ETSEC MAC2" }, |
| 41 | { 0x108, 0x03, "ETSEC MAC3" }, |
| 42 | { 0x10c, 0x04, "PEX1" }, |
| 43 | { 0x110, 0x05, "PEX2" }, |
| 44 | { 0x114, 0x06, "qDMA" }, |
| 45 | { 0x118, 0x07, "SATA" }, |
| 46 | { 0x11c, 0x08, "USB3" }, |
| 47 | { 0x120, 0x09, "QE" }, |
| 48 | { 0x124, 0x0a, "eSDHC" }, |
| 49 | { 0x128, 0x0b, "eMA" }, |
| 50 | { 0x14c, 0x0c, "2D-ACE" }, |
| 51 | { 0x150, 0x0d, "USB2" }, |
| 52 | { 0x18c, 0x0e, "DEBUG" }, |
| 53 | }; |
Yao Yuan | e0f8f54 | 2015-12-05 14:59:10 +0800 | [diff] [blame] | 54 | |
| 55 | unsigned int get_soc_major_rev(void) |
| 56 | { |
Tom Rini | 376b88a | 2022-10-28 20:27:13 -0400 | [diff] [blame] | 57 | struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); |
Yao Yuan | e0f8f54 | 2015-12-05 14:59:10 +0800 | [diff] [blame] | 58 | unsigned int svr, major; |
| 59 | |
| 60 | svr = in_be32(&gur->svr); |
| 61 | major = SVR_MAJ(svr); |
| 62 | |
| 63 | return major; |
| 64 | } |
| 65 | |
Ran Wang | 1509c8a | 2017-09-04 18:46:52 +0800 | [diff] [blame] | 66 | static void erratum_a009008(void) |
| 67 | { |
| 68 | #ifdef CONFIG_SYS_FSL_ERRATUM_A009008 |
| 69 | u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; |
| 70 | |
| 71 | clrsetbits_be32(scfg + SCFG_USB3PRM1CR / 4, |
| 72 | 0xF << 6, |
| 73 | SCFG_USB_TXVREFTUNE << 6); |
| 74 | #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */ |
| 75 | } |
| 76 | |
Ran Wang | d2b711b7 | 2017-09-04 18:46:53 +0800 | [diff] [blame] | 77 | static void erratum_a009798(void) |
| 78 | { |
| 79 | #ifdef CONFIG_SYS_FSL_ERRATUM_A009798 |
| 80 | u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; |
| 81 | |
| 82 | clrbits_be32(scfg + SCFG_USB3PRM1CR / 4, |
| 83 | SCFG_USB_SQRXTUNE_MASK << 23); |
| 84 | #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */ |
| 85 | } |
Ran Wang | 1509c8a | 2017-09-04 18:46:52 +0800 | [diff] [blame] | 86 | |
Ran Wang | 373a7b0 | 2017-09-04 18:46:54 +0800 | [diff] [blame] | 87 | static void erratum_a008997(void) |
| 88 | { |
| 89 | #ifdef CONFIG_SYS_FSL_ERRATUM_A008997 |
| 90 | u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; |
| 91 | |
| 92 | clrsetbits_be32(scfg + SCFG_USB3PRM2CR / 4, |
| 93 | SCFG_USB_PCSTXSWINGFULL_MASK, |
| 94 | SCFG_USB_PCSTXSWINGFULL_VAL); |
| 95 | #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */ |
| 96 | } |
| 97 | |
Ran Wang | 2eb4898 | 2017-09-04 18:46:55 +0800 | [diff] [blame] | 98 | static void erratum_a009007(void) |
| 99 | { |
| 100 | #ifdef CONFIG_SYS_FSL_ERRATUM_A009007 |
| 101 | void __iomem *usb_phy = (void __iomem *)USB_PHY_BASE; |
| 102 | |
| 103 | out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); |
| 104 | out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); |
| 105 | out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); |
| 106 | out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4); |
| 107 | #endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */ |
| 108 | } |
Ran Wang | 373a7b0 | 2017-09-04 18:46:54 +0800 | [diff] [blame] | 109 | |
Alison Wang | d6be97b | 2019-03-06 14:49:14 +0800 | [diff] [blame] | 110 | static void erratum_a008850_early(void) |
| 111 | { |
| 112 | #ifdef CONFIG_SYS_FSL_ERRATUM_A008850 |
| 113 | /* part 1 of 2 */ |
| 114 | struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + |
| 115 | CONFIG_SYS_CCI400_OFFSET); |
Tom Rini | 376b88a | 2022-10-28 20:27:13 -0400 | [diff] [blame] | 116 | struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR; |
Alison Wang | d6be97b | 2019-03-06 14:49:14 +0800 | [diff] [blame] | 117 | |
| 118 | /* disables propagation of barrier transactions to DDRC from CCI400 */ |
| 119 | out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); |
| 120 | |
| 121 | /* disable the re-ordering in DDRC */ |
| 122 | out_be32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); |
| 123 | #endif |
| 124 | } |
| 125 | |
| 126 | void erratum_a008850_post(void) |
| 127 | { |
| 128 | #ifdef CONFIG_SYS_FSL_ERRATUM_A008850 |
| 129 | /* part 2 of 2 */ |
| 130 | struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + |
| 131 | CONFIG_SYS_CCI400_OFFSET); |
Tom Rini | 376b88a | 2022-10-28 20:27:13 -0400 | [diff] [blame] | 132 | struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR; |
Alison Wang | d6be97b | 2019-03-06 14:49:14 +0800 | [diff] [blame] | 133 | u32 tmp; |
| 134 | |
| 135 | /* enable propagation of barrier transactions to DDRC from CCI400 */ |
| 136 | out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); |
| 137 | |
| 138 | /* enable the re-ordering in DDRC */ |
| 139 | tmp = in_be32(&ddr->eor); |
| 140 | tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); |
| 141 | out_be32(&ddr->eor, tmp); |
| 142 | #endif |
| 143 | } |
| 144 | |
Xiaoliang Yang | 73e0b01 | 2016-09-14 11:36:14 +0800 | [diff] [blame] | 145 | void s_init(void) |
| 146 | { |
| 147 | } |
| 148 | |
Hou Zhiqiang | 4b23ca8 | 2016-08-02 19:03:27 +0800 | [diff] [blame] | 149 | #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 |
| 150 | void erratum_a010315(void) |
| 151 | { |
| 152 | int i; |
| 153 | |
| 154 | for (i = PCIE1; i <= PCIE2; i++) |
| 155 | if (!is_serdes_configured(i)) { |
| 156 | debug("PCIe%d: disabled all R/W permission!\n", i); |
| 157 | set_pcie_ns_access(i, 0); |
| 158 | } |
| 159 | } |
| 160 | #endif |
| 161 | |
Yao Yuan | e0f8f54 | 2015-12-05 14:59:10 +0800 | [diff] [blame] | 162 | int arch_soc_init(void) |
| 163 | { |
Tom Rini | 376b88a | 2022-10-28 20:27:13 -0400 | [diff] [blame] | 164 | struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; |
Ashish Kumar | 1123406 | 2017-08-11 11:09:14 +0530 | [diff] [blame] | 165 | struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + |
| 166 | CONFIG_SYS_CCI400_OFFSET); |
Yao Yuan | e0f8f54 | 2015-12-05 14:59:10 +0800 | [diff] [blame] | 167 | unsigned int major; |
| 168 | |
Hou Zhiqiang | 5ac9a5c | 2016-08-02 19:03:23 +0800 | [diff] [blame] | 169 | #ifdef CONFIG_LAYERSCAPE_NS_ACCESS |
| 170 | enable_layerscape_ns_access(); |
| 171 | #endif |
| 172 | |
Mario Kicherer | 03ee72a | 2023-02-01 14:16:22 +0800 | [diff] [blame] | 173 | #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_SYS_FSL_QSPI_SKIP_CLKSEL) |
Yao Yuan | e0f8f54 | 2015-12-05 14:59:10 +0800 | [diff] [blame] | 174 | out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); |
| 175 | #endif |
| 176 | |
Yao Yuan | e0f8f54 | 2015-12-05 14:59:10 +0800 | [diff] [blame] | 177 | /* Configure Little endian for SAI, ASRC and SPDIF */ |
| 178 | out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE); |
| 179 | |
| 180 | /* |
| 181 | * Enable snoop requests and DVM message requests for |
Yao Yuan | 411fd29 | 2015-12-05 14:59:12 +0800 | [diff] [blame] | 182 | * All the slave insterfaces. |
Yao Yuan | e0f8f54 | 2015-12-05 14:59:10 +0800 | [diff] [blame] | 183 | */ |
Yao Yuan | 411fd29 | 2015-12-05 14:59:12 +0800 | [diff] [blame] | 184 | out_le32(&cci->slave[0].snoop_ctrl, |
| 185 | CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); |
| 186 | out_le32(&cci->slave[1].snoop_ctrl, |
| 187 | CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); |
| 188 | out_le32(&cci->slave[2].snoop_ctrl, |
| 189 | CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); |
Yao Yuan | e0f8f54 | 2015-12-05 14:59:10 +0800 | [diff] [blame] | 190 | out_le32(&cci->slave[4].snoop_ctrl, |
| 191 | CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); |
| 192 | |
| 193 | major = get_soc_major_rev(); |
| 194 | if (major == SOC_MAJOR_VER_1_0) { |
| 195 | /* |
| 196 | * Set CCI-400 Slave interface S1, S2 Shareable Override |
| 197 | * Register All transactions are treated as non-shareable |
| 198 | */ |
| 199 | out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); |
| 200 | out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); |
Yao Yuan | e0f8f54 | 2015-12-05 14:59:10 +0800 | [diff] [blame] | 201 | } |
| 202 | |
Yao Yuan | 1f28a4c | 2015-12-05 14:59:11 +0800 | [diff] [blame] | 203 | /* Enable all the snoop signal for various masters */ |
| 204 | out_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR | |
| 205 | SCFG_SNPCNFGCR_DCU_RD_WR | |
| 206 | SCFG_SNPCNFGCR_SATA_RD_WR | |
| 207 | SCFG_SNPCNFGCR_USB3_RD_WR | |
| 208 | SCFG_SNPCNFGCR_DBG_RD_WR | |
| 209 | SCFG_SNPCNFGCR_EDMA_SNP); |
| 210 | |
Yao Yuan | 96dae92 | 2015-12-05 14:59:13 +0800 | [diff] [blame] | 211 | /* |
| 212 | * Memory controller require a register write before being enabled. |
| 213 | * Affects: DDR |
| 214 | * Register: EDDRTQCFG |
| 215 | * Description: Memory controller performance is not optimal with |
| 216 | * default internal target queue register values. |
| 217 | * Workaround: Write a value of 63b2_0042h to address: 157_020Ch. |
| 218 | */ |
| 219 | out_be32(&scfg->eddrtqcfg, 0x63b20042); |
| 220 | |
Ran Wang | 1509c8a | 2017-09-04 18:46:52 +0800 | [diff] [blame] | 221 | /* Erratum */ |
Alison Wang | d6be97b | 2019-03-06 14:49:14 +0800 | [diff] [blame] | 222 | erratum_a008850_early(); |
Ran Wang | 1509c8a | 2017-09-04 18:46:52 +0800 | [diff] [blame] | 223 | erratum_a009008(); |
Ran Wang | d2b711b7 | 2017-09-04 18:46:53 +0800 | [diff] [blame] | 224 | erratum_a009798(); |
Ran Wang | 373a7b0 | 2017-09-04 18:46:54 +0800 | [diff] [blame] | 225 | erratum_a008997(); |
Ran Wang | 2eb4898 | 2017-09-04 18:46:55 +0800 | [diff] [blame] | 226 | erratum_a009007(); |
Ran Wang | 1509c8a | 2017-09-04 18:46:52 +0800 | [diff] [blame] | 227 | |
Yao Yuan | e0f8f54 | 2015-12-05 14:59:10 +0800 | [diff] [blame] | 228 | return 0; |
| 229 | } |
Alison Wang | 6936492 | 2016-02-05 12:48:17 +0800 | [diff] [blame] | 230 | |
| 231 | int ls102xa_smmu_stream_id_init(void) |
| 232 | { |
| 233 | ls1021x_config_caam_stream_id(sec_liodn_tbl, |
| 234 | ARRAY_SIZE(sec_liodn_tbl)); |
| 235 | |
| 236 | ls102xa_config_smmu_stream_id(dev_stream_id, |
| 237 | ARRAY_SIZE(dev_stream_id)); |
| 238 | |
| 239 | return 0; |
| 240 | } |