| Simon Glass | 45122ae | 2019-12-08 17:40:11 -0700 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright 2019 Google LLC |
| 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <dm.h> |
| 8 | #include <spl.h> |
| 9 | #include <asm/cpu.h> |
| 10 | #include <asm/cpu_common.h> |
| 11 | #include <asm/intel_regs.h> |
| 12 | #include <asm/io.h> |
| 13 | #include <asm/pci.h> |
| 14 | #include <asm/arch/systemagent.h> |
| 15 | |
| 16 | /* |
| 17 | * Punit Initialisation code. This all isn't documented, but |
| 18 | * this is the recipe. |
| 19 | */ |
| 20 | static int punit_init(struct udevice *dev) |
| 21 | { |
| 22 | struct udevice *cpu; |
| 23 | u32 reg; |
| 24 | ulong start; |
| 25 | int ret; |
| 26 | |
| 27 | /* Thermal throttle activation offset */ |
| 28 | ret = uclass_first_device_err(UCLASS_CPU, &cpu); |
| 29 | if (ret) |
| 30 | return log_msg_ret("Cannot find CPU", ret); |
| 31 | cpu_configure_thermal_target(cpu); |
| 32 | |
| 33 | /* |
| 34 | * Software Core Disable Mask (P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR). |
| 35 | * Enable all cores here. |
| 36 | */ |
| 37 | writel(0, MCHBAR_REG(CORE_DISABLE_MASK)); |
| 38 | |
| 39 | /* P-Unit bring up */ |
| 40 | reg = readl(MCHBAR_REG(BIOS_RESET_CPL)); |
| 41 | if (reg == 0xffffffff) { |
| 42 | /* P-unit not found */ |
| 43 | debug("Punit MMIO not available\n"); |
| 44 | return -ENOENT; |
| 45 | } |
| 46 | |
| 47 | /* Set Punit interrupt pin IPIN offset 3D */ |
| 48 | dm_pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x2); |
| 49 | |
| 50 | /* Set PUINT IRQ to 24 and INTPIN LOCK */ |
| 51 | writel(PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER | |
| 52 | PUINT_THERMAL_DEVICE_IRQ_LOCK, |
| 53 | MCHBAR_REG(PUNIT_THERMAL_DEVICE_IRQ)); |
| 54 | |
| 55 | /* Stage0 BIOS Reset Complete (RST_CPL) */ |
| 56 | enable_bios_reset_cpl(); |
| 57 | |
| 58 | /* |
| 59 | * Poll for bit 8 to check if PCODE has completed its action in response |
| 60 | * to BIOS Reset complete. We wait here till 1 ms for the bit to get |
| 61 | * set. |
| 62 | */ |
| 63 | start = get_timer(0); |
| 64 | while (!(readl(MCHBAR_REG(BIOS_RESET_CPL)) & PCODE_INIT_DONE)) { |
| 65 | if (get_timer(start) > 1) { |
| 66 | debug("PCODE Init Done timeout\n"); |
| 67 | return -ETIMEDOUT; |
| 68 | } |
| 69 | udelay(100); |
| 70 | } |
| 71 | debug("PUNIT init complete\n"); |
| 72 | |
| 73 | return 0; |
| 74 | } |
| 75 | |
| 76 | static int apl_punit_probe(struct udevice *dev) |
| 77 | { |
| 78 | if (spl_phase() == PHASE_SPL) |
| 79 | return punit_init(dev); |
| 80 | |
| 81 | return 0; |
| 82 | } |
| 83 | |
| 84 | static const struct udevice_id apl_syscon_ids[] = { |
| 85 | { .compatible = "intel,apl-punit", .data = X86_SYSCON_PUNIT }, |
| 86 | { } |
| 87 | }; |
| 88 | |
| 89 | U_BOOT_DRIVER(syscon_intel_punit) = { |
| 90 | .name = "intel_punit_syscon", |
| 91 | .id = UCLASS_SYSCON, |
| 92 | .of_match = apl_syscon_ids, |
| 93 | .probe = apl_punit_probe, |
| 94 | }; |