blob: cefc8157216d104f41800c41542f40b4173c92f1 [file] [log] [blame]
Paul Burton993ae662018-12-16 19:25:23 -03001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * CI20 configuration
4 *
5 * Copyright (c) 2013 Imagination Technologies
6 * Author: Paul Burton <paul.burton@imgtec.com>
7 */
8
9#ifndef __CONFIG_CI20_H__
10#define __CONFIG_CI20_H__
11
Paul Burton993ae662018-12-16 19:25:23 -030012/* Ingenic JZ4780 clock configuration. */
Paul Burton993ae662018-12-16 19:25:23 -030013#define CONFIG_SYS_MHZ 1200
14#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
15
16/* Memory configuration */
17#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
Paul Burton993ae662018-12-16 19:25:23 -030018#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
19
20#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */
21#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
Paul Burton993ae662018-12-16 19:25:23 -030022
23#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
24
25/* NS16550-ish UARTs */
26#define CONFIG_SYS_NS16550_CLK 48000000
27#define CONFIG_SYS_CONSOLE_IS_IN_ENV
28
29/* Ethernet: davicom DM9000 */
30#define CONFIG_DRIVER_DM9000 1
31#define CONFIG_DM9000_BASE 0xb6000000
32#define DM9000_IO CONFIG_DM9000_BASE
33#define DM9000_DATA (CONFIG_DM9000_BASE + 2)
34
Paul Burton993ae662018-12-16 19:25:23 -030035#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
36#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
37#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
38 /* Boot argument buffer size */
39#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
40
41/* Miscellaneous configuration options */
42#define CONFIG_SYS_BOOTM_LEN (64 << 20)
43
44/* SPL */
45#define CONFIG_SPL_STACK 0xf4008000 /* only max. 2KB spare! */
46
Paul Burton993ae662018-12-16 19:25:23 -030047#define CONFIG_SPL_MAX_SIZE ((14 * 1024) - 0xa00)
48
49#define CONFIG_SPL_BSS_START_ADDR 0xf4004000
50#define CONFIG_SPL_BSS_MAX_SIZE 0x00002000 /* 512KB, arbitrary */
51
52#define CONFIG_SPL_START_S_PATH "arch/mips/mach-jz47xx"
53
54#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1c /* 14 KiB offset */
55
56#endif /* __CONFIG_CI20_H__ */