Blame - arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds - filogic/uboot

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Stefan Roese	c6bc1db	2012-01-03 16:49:01 +0100	[diff] [blame]	1	/*
Stefan Roese	7618ad0	2015-08-18 09:27:17 +0200	[diff] [blame]	2	* Copyright (C) 2015 Stefan Roese <sr@denx.de>
				3	*
Stefan Roese	c6bc1db	2012-01-03 16:49:01 +0100	[diff] [blame]	4	* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
				5	* on behalf of DENX Software Engineering GmbH
				6	*
				7	* January 2004 - Changed to support H4 device
				8	* Copyright (c) 2004-2008 Texas Instruments
				9	*
				10	* (C) Copyright 2002
				11	* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
				12	*
Wolfgang Denk	d79de1d	2013-07-08 09:37:19 +0200	[diff] [blame]	13	* SPDX-License-Identifier: GPL-2.0+
Stefan Roese	c6bc1db	2012-01-03 16:49:01 +0100	[diff] [blame]	14	*/
				15
Stefan Roese	7618ad0	2015-08-18 09:27:17 +0200	[diff] [blame]	16	MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
				17	LENGTH = CONFIG_SPL_MAX_SIZE }
				18
Stefan Roese	c6bc1db	2012-01-03 16:49:01 +0100	[diff] [blame]	19	OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
				20	OUTPUT_ARCH(arm)
				21	ENTRY(_start)
				22	SECTIONS
				23	{
Stefan Roese	7618ad0	2015-08-18 09:27:17 +0200	[diff] [blame]	24	.text :
Stefan Roese	c6bc1db	2012-01-03 16:49:01 +0100	[diff] [blame]	25	{
Stefan Roese	7618ad0	2015-08-18 09:27:17 +0200	[diff] [blame]	26	__start = .;
Albert ARIBAUD	9852cc6	2014-04-15 16:13:51 +0200	[diff] [blame]	27	*(.vectors)
Stefan Roese	7618ad0	2015-08-18 09:27:17 +0200	[diff] [blame]	28	CPUDIR/spear/start.o (.text*)
Benoît Thébaudeau	3954db8	2013-04-11 09:36:03 +0000	[diff] [blame]	29	(.text)
Stefan Roese	7618ad0	2015-08-18 09:27:17 +0200	[diff] [blame]	30	} > .sram
Stefan Roese	c6bc1db	2012-01-03 16:49:01 +0100	[diff] [blame]	31
				32	. = ALIGN(4);
Stefan Roese	7618ad0	2015-08-18 09:27:17 +0200	[diff] [blame]	33	.rodata : { (SORT_BY_ALIGNMENT(.rodata)) } >.sram
Stefan Roese	c6bc1db	2012-01-03 16:49:01 +0100	[diff] [blame]	34
				35	. = ALIGN(4);
Stefan Roese	7618ad0	2015-08-18 09:27:17 +0200	[diff] [blame]	36	.data : { (SORT_BY_ALIGNMENT(.data)) } >.sram
Stefan Roese	c6bc1db	2012-01-03 16:49:01 +0100	[diff] [blame]	37
				38	. = ALIGN(4);
Stefan Roese	7618ad0	2015-08-18 09:27:17 +0200	[diff] [blame]	39	.u_boot_list : {
				40	KEEP((SORT(.u_boot_list)));
				41	} > .sram
Stefan Roese	c6bc1db	2012-01-03 16:49:01 +0100	[diff] [blame]	42
Stefan Roese	7618ad0	2015-08-18 09:27:17 +0200	[diff] [blame]	43	. = ALIGN(4);
				44	__image_copy_end = .;
				45	_end = .;
Stefan Roese	c6bc1db	2012-01-03 16:49:01 +0100	[diff] [blame]	46
Stefan Roese	7618ad0	2015-08-18 09:27:17 +0200	[diff] [blame]	47	.bss :
				48	{
Stefan Roese	c6bc1db	2012-01-03 16:49:01 +0100	[diff] [blame]	49	. = ALIGN(4);
				50	__bss_start = .;
				51	(.bss)
				52	. = ALIGN(4);
Simon Glass	ed70c8f	2013-03-14 06:54:53 +0000	[diff] [blame]	53	__bss_end = .;
Stefan Roese	7618ad0	2015-08-18 09:27:17 +0200	[diff] [blame]	54	} > .sram
Stefan Roese	c6bc1db	2012-01-03 16:49:01 +0100	[diff] [blame]	55	}