| Gregory CLEMENT | af05ee5 | 2018-12-14 16:16:47 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ |
| 2 | /* |
| 3 | * Copyright (c) 2018 Microsemi Corporation |
| 4 | */ |
| 5 | |
| 6 | #include <asm/asm.h> |
| 7 | #include <asm/regdef.h> |
| 8 | |
| 9 | .set noreorder |
| 10 | .extern vcoreiii_tlb_init |
| Lars Povlsen | 1470ce2 | 2020-02-06 10:45:40 +0100 | [diff] [blame] | 11 | .extern vcoreiii_ddr_init |
| Gregory CLEMENT | 819b5721 | 2018-12-14 16:16:48 +0100 | [diff] [blame] | 12 | #ifdef CONFIG_SOC_LUTON |
| 13 | .extern pll_init |
| 14 | #endif |
| Gregory CLEMENT | af05ee5 | 2018-12-14 16:16:47 +0100 | [diff] [blame] | 15 | |
| 16 | LEAF(lowlevel_init) |
| 17 | /* |
| 18 | * As we have no stack yet, we can assume the restricted |
| 19 | * luxury of the sX-registers without saving them |
| 20 | */ |
| Lars Povlsen | 1470ce2 | 2020-02-06 10:45:40 +0100 | [diff] [blame] | 21 | |
| 22 | /* Modify ra/s0 such we return to physical NOR location */ |
| 23 | li t0, 0x0fffffff |
| Simon Glass | 72cc538 | 2022-10-20 18:22:39 -0600 | [diff] [blame] | 24 | li t1, CONFIG_TEXT_BASE |
| Lars Povlsen | 1470ce2 | 2020-02-06 10:45:40 +0100 | [diff] [blame] | 25 | and s0, ra, t0 |
| 26 | add s0, s0, t1 |
| Gregory CLEMENT | af05ee5 | 2018-12-14 16:16:47 +0100 | [diff] [blame] | 27 | |
| 28 | jal vcoreiii_tlb_init |
| 29 | nop |
| Lars Povlsen | 1470ce2 | 2020-02-06 10:45:40 +0100 | [diff] [blame] | 30 | |
| Gregory CLEMENT | 819b5721 | 2018-12-14 16:16:48 +0100 | [diff] [blame] | 31 | #ifdef CONFIG_SOC_LUTON |
| 32 | jal pll_init |
| 33 | nop |
| 34 | #endif |
| Lars Povlsen | 1470ce2 | 2020-02-06 10:45:40 +0100 | [diff] [blame] | 35 | |
| 36 | /* Initialize DDR controller to enable stack/gd/heap */ |
| 37 | 0: |
| 38 | jal vcoreiii_ddr_init |
| 39 | nop |
| 40 | bnez v0, 0b /* Retry on error */ |
| 41 | nop |
| 42 | |
| Gregory CLEMENT | af05ee5 | 2018-12-14 16:16:47 +0100 | [diff] [blame] | 43 | jr s0 |
| 44 | nop |
| 45 | END(lowlevel_init) |