Stefan Roese | 7de9fc7 | 2007-10-05 17:11:30 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2000, 2001 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | * |
| 23 | */ |
| 24 | |
| 25 | /* |
| 26 | * ehnus: change pll frequency. |
| 27 | * Wed Sep 5 11:45:17 CST 2007 |
| 28 | * hsun@udtech.com.cn |
| 29 | */ |
| 30 | |
| 31 | |
| 32 | #include <common.h> |
| 33 | #include <config.h> |
| 34 | #include <command.h> |
| 35 | #include <i2c.h> |
| 36 | |
| 37 | #ifdef CONFIG_CMD_EEPROM |
| 38 | |
| 39 | #define EEPROM_CONF_OFFSET 0 |
| 40 | #define EEPROM_TEST_OFFSET 16 |
| 41 | #define EEPROM_SDSTP_PARAM 16 |
| 42 | |
| 43 | #define PLL_NAME_MAX 12 |
| 44 | #define BUF_STEP 8 |
| 45 | |
| 46 | /* eeprom_wirtes 8Byte per op. */ |
| 47 | #define EEPROM_ALTER_FREQ(freq) \ |
| 48 | do { \ |
| 49 | int __i; \ |
| 50 | for (__i = 0; __i < 2; __i++) \ |
| 51 | eeprom_write (CFG_I2C_EEPROM_ADDR, \ |
| 52 | EEPROM_CONF_OFFSET + __i*BUF_STEP, \ |
| 53 | pll_select[freq], \ |
| 54 | BUF_STEP + __i*BUF_STEP); \ |
| 55 | } while (0) |
| 56 | |
| 57 | #define PDEBUG |
| 58 | #ifdef PDEBUG |
| 59 | #define PLL_DEBUG pll_debug(EEPROM_CONF_OFFSET) |
| 60 | #else |
| 61 | #define PLL_DEBUG |
| 62 | #endif |
| 63 | |
| 64 | typedef enum { |
| 65 | PLL_ebc20, |
| 66 | PLL_333, |
| 67 | PLL_4001, |
| 68 | PLL_4002, |
| 69 | PLL_533, |
| 70 | PLL_600, |
| 71 | PLL_666, /* For now, kilauea can't support */ |
| 72 | RCONF, |
| 73 | WTEST, |
| 74 | PLL_TOTAL |
| 75 | } pll_freq_t; |
| 76 | |
| 77 | static const char |
| 78 | pll_name[][PLL_NAME_MAX] = { |
| 79 | "PLL_ebc20", |
| 80 | "PLL_333", |
| 81 | "PLL_400@1", |
| 82 | "PLL_400@2", |
| 83 | "PLL_533", |
| 84 | "PLL_600", |
| 85 | "PLL_666", |
| 86 | "RCONF", |
| 87 | "WTEST", |
| 88 | "" |
| 89 | }; |
| 90 | |
| 91 | /* |
| 92 | * ehnus: |
| 93 | */ |
| 94 | static uchar |
| 95 | pll_select[][EEPROM_SDSTP_PARAM] = { |
| 96 | /* 0: CPU 333MHz EBC 20MHz, for test only */ |
| 97 | { |
| 98 | 0x8c, 0x12, 0xec, 0x12, 0x88, 0x00, 0x0a, 0x00, |
| 99 | 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 |
| 100 | }, |
| 101 | |
| 102 | /* 0: 333 */ |
| 103 | { |
| 104 | 0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00, |
| 105 | 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 |
| 106 | }, |
| 107 | |
| 108 | /* 1: 400_266 */ |
| 109 | { |
| 110 | 0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00, |
| 111 | 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 |
| 112 | }, |
| 113 | |
| 114 | /* 2: 400 */ |
| 115 | { |
| 116 | 0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00, |
| 117 | 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 |
| 118 | }, |
| 119 | |
| 120 | /* 3: 533 */ |
| 121 | { |
| 122 | 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00, |
| 123 | 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 |
| 124 | }, |
| 125 | |
| 126 | /* 4: 600 */ |
| 127 | { |
| 128 | 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00, |
| 129 | 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 |
| 130 | }, |
| 131 | |
| 132 | /* 5: 666 */ |
| 133 | { |
| 134 | 0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00, |
| 135 | 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 |
| 136 | }, |
| 137 | |
| 138 | {} |
| 139 | }; |
| 140 | |
| 141 | static uchar |
| 142 | testbuf[EEPROM_SDSTP_PARAM] = { |
| 143 | 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, |
| 144 | 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff |
| 145 | }; |
| 146 | |
| 147 | static void |
| 148 | pll_debug(int off) |
| 149 | { |
| 150 | int i; |
| 151 | uchar buffer[EEPROM_SDSTP_PARAM]; |
| 152 | |
| 153 | memset(buffer, 0, sizeof(buffer)); |
| 154 | eeprom_read(CFG_I2C_EEPROM_ADDR, off, |
| 155 | buffer, EEPROM_SDSTP_PARAM); |
| 156 | |
| 157 | printf("Debug: SDSTP[0-3] at offset \"0x%02x\" lists as follows: \n", off); |
| 158 | for (i = 0; i < EEPROM_SDSTP_PARAM; i++) |
| 159 | printf("%02x ", buffer[i]); |
| 160 | printf("\n"); |
| 161 | } |
| 162 | |
| 163 | static void |
| 164 | test_write(void) |
| 165 | { |
| 166 | printf("Debug: test eeprom_write ... "); |
| 167 | |
| 168 | /* |
| 169 | * Write twice, 8 bytes per write |
| 170 | */ |
| 171 | eeprom_write (CFG_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET, |
| 172 | testbuf, 8); |
| 173 | eeprom_write (CFG_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET+8, |
| 174 | testbuf, 16); |
| 175 | printf("done\n"); |
| 176 | |
| 177 | pll_debug(EEPROM_TEST_OFFSET); |
| 178 | } |
| 179 | |
| 180 | int |
| 181 | do_pll_alter (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
| 182 | { |
| 183 | char c = '\0'; |
| 184 | pll_freq_t pll_freq; |
| 185 | if (argc < 2) { |
| 186 | printf("Usage: \n%s\n", cmdtp->usage); |
| 187 | goto ret; |
| 188 | } |
| 189 | |
| 190 | for (pll_freq = PLL_ebc20; pll_freq < PLL_TOTAL; pll_freq++) |
| 191 | if (!strcmp(pll_name[pll_freq], argv[1])) |
| 192 | break; |
| 193 | |
| 194 | switch (pll_freq) { |
| 195 | case PLL_ebc20: |
| 196 | case PLL_333: |
| 197 | case PLL_4001: |
| 198 | case PLL_4002: |
| 199 | case PLL_533: |
| 200 | case PLL_600: |
| 201 | EEPROM_ALTER_FREQ(pll_freq); |
| 202 | break; |
| 203 | |
| 204 | case PLL_666: /* not support */ |
| 205 | printf("Choose this option will result in a boot failure." |
| 206 | "\nContinue? (Y/N): "); |
| 207 | |
| 208 | c = getc(); putc('\n'); |
| 209 | |
| 210 | if ((c == 'y') || (c == 'Y')) { |
| 211 | EEPROM_ALTER_FREQ(pll_freq); |
| 212 | break; |
| 213 | } |
| 214 | goto ret; |
| 215 | |
| 216 | case RCONF: |
| 217 | pll_debug(EEPROM_CONF_OFFSET); |
| 218 | goto ret; |
| 219 | case WTEST: |
| 220 | printf("DEBUG: write test\n"); |
| 221 | test_write(); |
| 222 | goto ret; |
| 223 | |
| 224 | default: |
| 225 | printf("Invalid options" |
| 226 | "\n\nUsage: \n%s\n", cmdtp->usage); |
| 227 | goto ret; |
| 228 | } |
| 229 | |
| 230 | printf("PLL set to %s, " |
| 231 | "reset the board to take effect\n", pll_name[pll_freq]); |
| 232 | |
| 233 | PLL_DEBUG; |
| 234 | ret: |
| 235 | return 0; |
| 236 | } |
| 237 | |
| 238 | U_BOOT_CMD( |
| 239 | pllalter, CFG_MAXARGS, 1, do_pll_alter, |
| 240 | "pllalter- change pll frequence \n", |
| 241 | "pllalter <selection> - change pll frequence \n\n\ |
| 242 | ** New freq take effect after reset. ** \n\ |
| 243 | ----------------------------------------------\n\ |
| 244 | PLL_ebc20: Board: AMCC 405EX(r) Evaluation Board\n\ |
| 245 | \t Same as PLL_333 \n\ |
| 246 | \t except \n\ |
| 247 | \t EBC: 20 MHz \n\ |
| 248 | ----------------------------------------------\n\ |
| 249 | PLL_333: Board: AMCC 405EX(r) Evaluation Board\n\ |
| 250 | \t VCO: 666 MHz \n\ |
| 251 | \t CPU: 333 MHz \n\ |
| 252 | \t PLB: 166 MHz \n\ |
| 253 | \t OPB: 83 MHz \n\ |
| 254 | \t DDR: 83 MHz \n\ |
| 255 | ------------------------------------------------\n\ |
| 256 | PLL_400@1: Board: AMCC 405EX(r) Evaluation Board\n\ |
| 257 | \t VCO: 800 MHz \n\ |
| 258 | \t CPU: 400 MHz \n\ |
| 259 | \t PLB: 133 MHz \n\ |
| 260 | \t OPB: 66 MHz \n\ |
| 261 | \t DDR: 133 MHz \n\ |
| 262 | ------------------------------------------------\n\ |
| 263 | PLL_400@2: Board: AMCC 405EX(r) Evaluation Board\n\ |
| 264 | \t VCO: 800 MHz \n\ |
| 265 | \t CPU: 400 MHz \n\ |
| 266 | \t PLB: 200 MHz \n\ |
| 267 | \t OPB: 100 MHz \n\ |
| 268 | \t DDR: 200 MHz \n\ |
| 269 | ----------------------------------------------\n\ |
| 270 | PLL_533: Board: AMCC 405EX(r) Evaluation Board\n\ |
| 271 | \t VCO: 1066 MHz \n\ |
| 272 | \t CPU: 533 MHz \n\ |
| 273 | \t PLB: 177 MHz \n\ |
| 274 | \t OPB: 88 MHz \n\ |
| 275 | \t DDR: 177 MHz \n\ |
| 276 | ----------------------------------------------\n\ |
| 277 | PLL_600: Board: AMCC 405EX(r) Evaluation Board\n\ |
| 278 | \t VCO: 1200 MHz \n\ |
| 279 | \t CPU: 600 MHz \n\ |
| 280 | \t PLB: 200 MHz \n\ |
| 281 | \t OPB: 100 MHz \n\ |
| 282 | \t DDR: 200 MHz \n\ |
| 283 | ----------------------------------------------\n\ |
| 284 | PLL_666: Board: AMCC 405EX(r) Evaluation Board\n\ |
| 285 | \t VCO: 1333 MHz \n\ |
| 286 | \t CPU: 666 MHz \n\ |
| 287 | \t PLB: 166 MHz \n\ |
| 288 | \t OPB: 83 MHz \n\ |
| 289 | \t DDR: 166 MHz \n\ |
| 290 | -----------------------------------------------\n\ |
| 291 | RCONF: Read current eeprom configuration. \n\ |
| 292 | -----------------------------------------------\n\ |
| 293 | WTEST: Test EEPROM write with predefined values\n\ |
| 294 | -----------------------------------------------\n" |
| 295 | ); |
| 296 | |
Stefan Roese | e2a1242f | 2008-01-17 07:50:17 +0100 | [diff] [blame] | 297 | #endif /* CONFIG_CMD_EEPROM */ |