doc/device-tree-bindings/misc/intel,baytrail-fsp.txt

Intel Bay Trail FSP UPD Binding
===============================

The device tree node which describes the overriding of the Intel Bay Trail FSP
UPD data for configuring the SoC.

All properties can be found within the `upd-region` struct in
arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h, under the same names, and in
Intel's FSP Binary Configuration Tool for Bay Trail.  This list of properties is
matched up to Intel's E3800 FSPv4 release.

# Boolean properties:

- fsp,enable-sdio
- fsp,enable-sdcard
- fsp,enable-hsuart0
- fsp,enable-hsuart1
- fsp,enable-spi
- fsp,enable-sata
- fsp,enable-azalia
- fsp,enable-xhci
- fsp,enable-lpe
- fsp,lpss-sio-enable-pci-mode
- fsp,enable-dma0
- fsp,enable-dma1
- fsp,enable-i2-c0
- fsp,enable-i2-c1
- fsp,enable-i2-c2
- fsp,enable-i2-c3
- fsp,enable-i2-c4
- fsp,enable-i2-c5
- fsp,enable-i2-c6
- fsp,enable-pwm0
- fsp,enable-pwm1
- fsp,enable-hsi
- fsp,mrc-debug-msg
- fsp,isp-enable
- fsp,scc-enable-pci-mode
- fsp,igd-render-standby
- fsp,txe-uma-enable
- fsp,emmc45-ddr50-enabled
- fsp,emmc45-hs200-enabled
- fsp,enable-igd
- fsp,enable-memory-down

If you set "fsp,enable-memory-down" you are strongly encouraged to provide an
"fsp,memory-down-params{};" to specify how your memory is configured.  If you do
not set "fsp,enable-memory-down", then the DIMM SPD information will be
discovered by the FSP and used to setup main memory.


# Integer properties:

- fsp,mrc-init-tseg-size
- fsp,mrc-init-mmio-size
- fsp,mrc-init-spd-addr1
- fsp,mrc-init-spd-addr2
- fsp,emmc-boot-mode
- fsp,sata-mode
- fsp,igd-dvmt50-pre-alloc
- fsp,aperture-size
- fsp,gtt-size
- fsp,serial-debug-port-address
- fsp,serial-debug-port-type
- fsp,os-selection
- fsp,emmc45-retune-timer-value

- fsp,memory-down-params {

	# Boolean properties:

	- fsp,dimm-0-enable
	- fsp,dimm-1-enable

	# Integer properties:

	- fsp,dram-speed:
	  0x0: "800 MHz"
	  0x1: "1066 MHz"
	  0x2: "1333 MHz"
	  0x3: "1600 MHz"

	- fsp,dram-type
	  0x0: "DDR3"
	  0x1: "DDR3L"
	  0x2: "DDR3U"
	  0x4: "LPDDR2"
	  0x5: "LPDDR3"
	  0x6: "DDR4"

	- fsp,dimm-width
	  0x0: "x8"
	  0x1: "x16"
	  0x2: "x32"

	- fsp,dimm-density
	  0x0: "1 Gbit"
	  0x1: "2 Gbit"
	  0x2: "4 Gbit"
	  0x3: "8 Gbit"

	- fsp,dimm-bus-width
	  0x0: "8 bits"
	  0x1: "16 bits"
	  0x2: "32 bits"
	  0x3: "64 bits"

	- fsp,dimm-sides
	  0x0: "1 rank"
	  0x1: "2 ranks"

	- fsp,dimm-tcl
	- fsp,dimm-trpt-rcd
	- fsp,dimm-twr
	- fsp,dimm-twtr
	- fsp,dimm-trrd
	- fsp,dimm-trtp
	- fsp,dimm-tfaw
};


Example (from MinnowMax Dual Core):
-----------------------------------

/ {
	...

	fsp {
		compatible = "intel,baytrail-fsp";
		fsp,mrc-init-tseg-size = <0>;
		fsp,mrc-init-mmio-size = <0x800>;
		fsp,mrc-init-spd-addr1 = <0xa0>;
		fsp,mrc-init-spd-addr2 = <0xa2>;
		fsp,emmc-boot-mode = <2>;
		fsp,enable-sdio;
		fsp,enable-sdcard;
		fsp,enable-hsuart1;
		fsp,enable-spi;
		fsp,enable-sata;
		fsp,sata-mode = <1>;
		fsp,enable-xhci;
		fsp,enable-lpe;
		fsp,lpss-sio-enable-pci-mode;
		fsp,enable-dma0;
		fsp,enable-dma1;
		fsp,enable-i2c0;
		fsp,enable-i2c1;
		fsp,enable-i2c2;
		fsp,enable-i2c3;
		fsp,enable-i2c4;
		fsp,enable-i2c5;
		fsp,enable-i2c6;
		fsp,enable-pwm0;
		fsp,enable-pwm1;
		fsp,igd-dvmt50-pre-alloc = <2>;
		fsp,aperture-size = <2>;
		fsp,gtt-size = <2>;
		fsp,serial-debug-port-address = <0x3f8>;
		fsp,serial-debug-port-type = <1>;
		fsp,mrc-debug-msg;
		fsp,scc-enable-pci-mode;
		fsp,os-selection = <4>;
		fsp,emmc45-ddr50-enabled;
		fsp,emmc45-retune-timer-value = <8>;
		fsp,enable-igd;
		fsp,enable-memory-down;
		fsp,memory-down-params {
			compatible = "intel,baytrail-fsp-mdp";
			fsp,dram-speed = <1>;
			fsp,dram-type = <1>;
			fsp,dimm-0-enable;
			fsp,dimm-width = <1>;
			fsp,dimm-density = <2>;
			fsp,dimm-bus-width = <3>;
			fsp,dimm-sides = <0>;
			fsp,dimm-tcl = <0xb>;
			fsp,dimm-trpt-rcd = <0xb>;
			fsp,dimm-twr = <0xc>;
			fsp,dimm-twtr = <6>;
			fsp,dimm-trrd = <6>;
			fsp,dimm-trtp = <6>;
			fsp,dimm-tfaw = <0x14>;
		};
	};

	...
};