| Stefan Agner | 1ad129a | 2016-10-05 15:27:06 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2016 Toradex AG |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ or X11 |
| 5 | */ |
| 6 | |
| 7 | /dts-v1/; |
| 8 | #include <dt-bindings/gpio/gpio.h> |
| 9 | #include "imx7.dtsi" |
| 10 | |
| 11 | / { |
| 12 | model = "Toradex Colibri iMX7S/D"; |
| 13 | compatible = "toradex,imx7-colibri", "fsl,imx7"; |
| 14 | |
| 15 | chosen { |
| 16 | stdout-path = &uart1; |
| 17 | }; |
| 18 | }; |
| 19 | |
| 20 | &i2c1 { |
| 21 | pinctrl-names = "default", "gpio"; |
| 22 | pinctrl-0 = <&pinctrl_i2c1>; |
| 23 | pinctrl-1 = <&pinctrl_i2c1_gpio>; |
| 24 | sda-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; |
| 25 | scl-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; |
| 26 | status = "okay"; |
| Stefan Agner | fd8bb69 | 2016-10-05 15:27:10 -0700 | [diff] [blame] | 27 | |
| 28 | rn5t567@33 { |
| 29 | compatible = "ricoh,rn5t567"; |
| 30 | reg = <0x33>; |
| 31 | }; |
| Stefan Agner | 1ad129a | 2016-10-05 15:27:06 -0700 | [diff] [blame] | 32 | }; |
| 33 | |
| 34 | &i2c4 { |
| 35 | pinctrl-names = "default", "gpio"; |
| 36 | pinctrl-0 = <&pinctrl_i2c4>; |
| 37 | pinctrl-1 = <&pinctrl_i2c4_gpio>; |
| 38 | sda-gpios = <&gpio7 9 GPIO_ACTIVE_LOW>; |
| 39 | scl-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>; |
| 40 | status = "okay"; |
| 41 | }; |
| 42 | |
| 43 | &uart1 { |
| 44 | pinctrl-names = "default"; |
| 45 | pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>; |
| 46 | uart-has-rtscts; |
| 47 | fsl,dte-mode; |
| 48 | status = "okay"; |
| 49 | }; |
| 50 | |
| 51 | &iomuxc { |
| 52 | pinctrl_i2c4: i2c4-grp { |
| 53 | fsl,pins = < |
| 54 | MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f |
| 55 | MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f |
| 56 | >; |
| 57 | }; |
| 58 | |
| 59 | pinctrl_i2c4_gpio: i2c4-gpio-grp { |
| 60 | fsl,pins = < |
| 61 | MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x4000007f |
| 62 | MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x4000007f |
| 63 | >; |
| 64 | }; |
| 65 | |
| 66 | pinctrl_uart1: uart1-grp { |
| 67 | fsl,pins = < |
| 68 | MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x79 |
| 69 | MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x79 |
| 70 | MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x79 |
| 71 | MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x79 |
| 72 | >; |
| 73 | }; |
| 74 | |
| 75 | pinctrl_uart1_ctrl1: uart1-ctrl1-grp { |
| 76 | fsl,pins = < |
| 77 | MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x14 /* DCD */ |
| 78 | MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x14 /* DTR */ |
| 79 | >; |
| 80 | }; |
| 81 | }; |
| 82 | |
| 83 | &iomuxc_lpsr { |
| 84 | pinctrl_i2c1: i2c1-grp { |
| 85 | fsl,pins = < |
| 86 | MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x4000007f |
| 87 | MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f |
| 88 | >; |
| 89 | }; |
| 90 | |
| 91 | pinctrl_i2c1_gpio: i2c1-gpio-grp { |
| 92 | fsl,pins = < |
| 93 | MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x4000007f |
| 94 | MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x4000007f |
| 95 | >; |
| 96 | }; |
| 97 | }; |