Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Peter Tyser | 1c2b329 | 2008-12-17 16:36:23 -0600 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2008 Extreme Engineering Solutions, Inc. |
| 4 | * Copyright 2008 Freescale Semiconductor, Inc. |
Peter Tyser | 1c2b329 | 2008-12-17 16:36:23 -0600 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <i2c.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 9 | #include <log.h> |
Peter Tyser | 1c2b329 | 2008-12-17 16:36:23 -0600 | [diff] [blame] | 10 | |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 11 | #include <fsl_ddr_sdram.h> |
| 12 | #include <fsl_ddr_dimm_params.h> |
Peter Tyser | 1c2b329 | 2008-12-17 16:36:23 -0600 | [diff] [blame] | 13 | |
Kumar Gala | c68e86c | 2011-01-31 22:18:47 -0600 | [diff] [blame] | 14 | void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address) |
Peter Tyser | 1c2b329 | 2008-12-17 16:36:23 -0600 | [diff] [blame] | 15 | { |
| 16 | i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd, |
| 17 | sizeof(ddr2_spd_eeprom_t)); |
| 18 | } |
| 19 | |
Peter Tyser | 1c2b329 | 2008-12-17 16:36:23 -0600 | [diff] [blame] | 20 | /* |
| 21 | * There are four board-specific SDRAM timing parameters which must be |
| 22 | * calculated based on the particular PCB artwork. These are: |
| 23 | * 1.) CPO (Read Capture Delay) |
| 24 | * - TIMING_CFG_2 register |
| 25 | * Source: Calculation based on board trace lengths and |
| 26 | * chip-specific internal delays. |
| 27 | * 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay) |
| 28 | * - TIMING_CFG_2 register |
| 29 | * Source: Calculation based on board trace lengths. |
| 30 | * Unless clock and DQ lanes are very different |
| 31 | * lengths (>2"), this should be set to the nominal value |
| 32 | * of 1/2 clock delay. |
| 33 | * 3.) CLK_ADJUST (Clock and Addr/Cmd alignment control) |
| 34 | * - DDR_SDRAM_CLK_CNTL register |
| 35 | * Source: Signal Integrity Simulations |
| 36 | * 4.) 2T Timing on Addr/Ctl |
| 37 | * - TIMING_CFG_2 register |
| 38 | * Source: Signal Integrity Simulations |
| 39 | * Usually only needed with heavy load/very high speed (>DDR2-800) |
| 40 | * |
| 41 | * ====== XPedite5370 DDR2-600 read delay calculations ====== |
| 42 | * |
| 43 | * See Freescale's App Note AN2583 as refrence. This document also |
| 44 | * contains the chip-specific delays for 8548E, 8572, etc. |
| 45 | * |
| 46 | * For MPC8572E |
| 47 | * Minimum chip delay (Ch 0): 1.372ns |
| 48 | * Maximum chip delay (Ch 0): 2.914ns |
| 49 | * Minimum chip delay (Ch 1): 1.220ns |
| 50 | * Maximum chip delay (Ch 1): 2.595ns |
| 51 | * |
| 52 | * CLK adjust = 5 (from simulations) = 5/8* 3.33ns = 2080ps |
| 53 | * |
| 54 | * Minimum delay calc (Ch 0): |
| 55 | * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly |
| 56 | * 2.3" * 180 - 400ps + 1.9" * 180 + 2080ps + 1372ps |
| 57 | * = 3808ps |
| 58 | * = 3.808ns |
| 59 | * |
| 60 | * Maximum delay calc (Ch 0): |
| 61 | * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly |
| 62 | * 2.3" * 180 + 400ps + 2.4" * 180 + 2080ps + 2914ps |
| 63 | * = 6240ps |
| 64 | * = 6.240ns |
| 65 | * |
| 66 | * Minimum delay calc (Ch 1): |
| 67 | * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly |
| 68 | * 1.46" * 180- 400ps + 0.7" * 180 + 2080ps + 1220ps |
| 69 | * = 3288ps |
| 70 | * = 3.288ns |
| 71 | * |
| 72 | * Maximum delay calc (Ch 1): |
| 73 | * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly |
| 74 | * 1.46" * 180+ 400ps + 1.1" * 180 + 2080ps + 2595ps |
| 75 | * = 5536ps |
| 76 | * = 5.536ns |
| 77 | * |
| 78 | * Ch.0: 3.808ns to 6.240ns additional delay needed (pick 5ns as target) |
| 79 | * This is 1.5 clock cycles, pick CPO = READ_LAT + 3/2 (0x8) |
| 80 | * Ch.1: 3.288ns to 5.536ns additional delay needed (pick 4.4ns as target) |
| 81 | * This is 1.32 clock cycles, pick CPO = READ_LAT + 5/4 (0x7) |
| 82 | * |
| 83 | * |
| 84 | * ====== XPedite5370 DDR2-800 read delay calculations ====== |
| 85 | * |
| 86 | * See Freescale's App Note AN2583 as refrence. This document also |
| 87 | * contains the chip-specific delays for 8548E, 8572, etc. |
| 88 | * |
| 89 | * For MPC8572E |
| 90 | * Minimum chip delay (Ch 0): 1.372ns |
| 91 | * Maximum chip delay (Ch 0): 2.914ns |
| 92 | * Minimum chip delay (Ch 1): 1.220ns |
| 93 | * Maximum chip delay (Ch 1): 2.595ns |
| 94 | * |
| 95 | * CLK adjust = 5 (from simulations) = 5/8* 2.5ns = 1563ps |
| 96 | * |
| 97 | * Minimum delay calc (Ch 0): |
| 98 | * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly |
| 99 | * 2.3" * 180 - 350ps + 1.9" * 180 + 1563ps + 1372ps |
| 100 | * = 3341ps |
| 101 | * = 3.341ns |
| 102 | * |
| 103 | * Maximum delay calc (Ch 0): |
| 104 | * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly |
| 105 | * 2.3" * 180 + 350ps + 2.4" * 180 + 1563ps + 2914ps |
| 106 | * = 5673ps |
| 107 | * = 5.673ns |
| 108 | * |
| 109 | * Minimum delay calc (Ch 1): |
| 110 | * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly |
| 111 | * 1.46" * 180- 350ps + 0.7" * 180 + 1563ps + 1220ps |
| 112 | * = 2822ps |
| 113 | * = 2.822ns |
| 114 | * |
| 115 | * Maximum delay calc (Ch 1): |
| 116 | * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly |
| 117 | * 1.46" * 180+ 350ps + 1.1" * 180 + 1563ps + 2595ps |
| 118 | * = 4968ps |
| 119 | * = 4.968ns |
| 120 | * |
| 121 | * Ch.0: 3.341ns to 5.673ns additional delay needed (pick 4.5ns as target) |
| 122 | * This is 1.8 clock cycles, pick CPO = READ_LAT + 7/4 (0x9) |
| 123 | * Ch.1: 2.822ns to 4.968ns additional delay needed (pick 3.9ns as target) |
| 124 | * This is 1.56 clock cycles, pick CPO = READ_LAT + 3/2 (0x8) |
| 125 | * |
| 126 | * Write latency (WR_DATA_DELAY) is calculated by doing the following: |
| 127 | * |
| 128 | * The DDR SDRAM specification requires DQS be received no sooner than |
| 129 | * 75% of an SDRAM clock period—and no later than 125% of a clock |
| 130 | * period—from the capturing clock edge of the command/address at the |
| 131 | * SDRAM. |
| 132 | * |
| 133 | * Based on the above tracelengths, the following are calculated: |
| 134 | * Ch. 0 8572 to DRAM propagation (DQ lanes) : 1.9" * 180 = 0.342ns |
| 135 | * Ch. 0 8572 to DRAM propagation (CLKs) : 2.3" * 180 = 0.414ns |
| 136 | * Ch. 1 8572 to DRAM propagation (DQ lanes) : 0.7" * 180 = 0.126ns |
| 137 | * Ch. 1 8572 to DRAM propagation (CLKs ) : 1.47" * 180 = 0.264ns |
| 138 | * |
| 139 | * Difference in arrival time CLK vs. DQS: |
| 140 | * Ch. 0 0.072ns |
| 141 | * Ch. 1 0.138ns |
| 142 | * |
| 143 | * Both of these values are much less than 25% of the clock |
| 144 | * period at DDR2-600 or DDR2-800, so no additional delay is needed over |
| 145 | * the 1/2 cycle which normally aligns the first DQS transition |
| 146 | * exactly WL (CAS latency minus one cycle) after the CAS strobe. |
| 147 | * See Figure 9-53 in MPC8572E manual: "1/2 delay" in Freescale's |
| 148 | * terminology corresponds to exactly one clock period delay after |
| 149 | * the CAS strobe. (due to the fact that the "delay" is referenced |
| 150 | * from the *falling* edge of the CLK, just after the rising edge |
| 151 | * which the CAS strobe is latched on. |
| 152 | */ |
| 153 | |
| 154 | typedef struct board_memctl_options { |
| 155 | uint16_t datarate_mhz_low; |
| 156 | uint16_t datarate_mhz_high; |
| 157 | uint8_t clk_adjust; |
| 158 | uint8_t cpo_override; |
| 159 | uint8_t write_data_delay; |
| 160 | } board_memctl_options_t; |
| 161 | |
| 162 | static struct board_memctl_options bopts_ctrl[][2] = { |
| 163 | { |
| 164 | /* Controller 0 */ |
| 165 | { |
| 166 | /* DDR2 600/667 */ |
| 167 | .datarate_mhz_low = 500, |
| 168 | .datarate_mhz_high = 750, |
| 169 | .clk_adjust = 5, |
| 170 | .cpo_override = 8, |
| 171 | .write_data_delay = 2, |
| 172 | }, |
| 173 | { |
| 174 | /* DDR2 800 */ |
| 175 | .datarate_mhz_low = 750, |
| 176 | .datarate_mhz_high = 850, |
| 177 | .clk_adjust = 5, |
| 178 | .cpo_override = 9, |
| 179 | .write_data_delay = 2, |
| 180 | }, |
| 181 | }, |
| 182 | { |
| 183 | /* Controller 1 */ |
| 184 | { |
| 185 | /* DDR2 600/667 */ |
| 186 | .datarate_mhz_low = 500, |
| 187 | .datarate_mhz_high = 750, |
| 188 | .clk_adjust = 5, |
| 189 | .cpo_override = 7, |
| 190 | .write_data_delay = 2, |
| 191 | }, |
| 192 | { |
| 193 | /* DDR2 800 */ |
| 194 | .datarate_mhz_low = 750, |
| 195 | .datarate_mhz_high = 850, |
| 196 | .clk_adjust = 5, |
| 197 | .cpo_override = 8, |
| 198 | .write_data_delay = 2, |
| 199 | }, |
| 200 | }, |
| 201 | }; |
| 202 | |
| 203 | void fsl_ddr_board_options(memctl_options_t *popts, |
| 204 | dimm_params_t *pdimm, |
| 205 | unsigned int ctrl_num) |
| 206 | { |
| 207 | struct board_memctl_options *bopts = bopts_ctrl[ctrl_num]; |
| 208 | sys_info_t sysinfo; |
| 209 | int i; |
| 210 | unsigned int datarate; |
| 211 | |
| 212 | get_sys_info(&sysinfo); |
Prabhakar Kushwaha | d169808 | 2013-08-16 14:52:26 +0530 | [diff] [blame] | 213 | datarate = sysinfo.freq_ddrbus / 1000 / 1000; |
Peter Tyser | 1c2b329 | 2008-12-17 16:36:23 -0600 | [diff] [blame] | 214 | |
| 215 | for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) { |
| 216 | if ((bopts[i].datarate_mhz_low <= datarate) && |
| 217 | (bopts[i].datarate_mhz_high >= datarate)) { |
| 218 | debug("controller %d:\n", ctrl_num); |
| 219 | debug(" clk_adjust = %d\n", bopts[i].clk_adjust); |
| 220 | debug(" cpo = %d\n", bopts[i].cpo_override); |
| 221 | debug(" write_data_delay = %d\n", |
| 222 | bopts[i].write_data_delay); |
| 223 | popts->clk_adjust = bopts[i].clk_adjust; |
| 224 | popts->cpo_override = bopts[i].cpo_override; |
| 225 | popts->write_data_delay = bopts[i].write_data_delay; |
| 226 | } |
| 227 | } |
| 228 | |
| 229 | /* |
| 230 | * Factors to consider for half-strength driver enable: |
| 231 | * - number of DIMMs installed |
| 232 | */ |
| 233 | popts->half_strength_driver_enable = 0; |
| 234 | } |