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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Masahiro Yamada2aa4b5b2016-10-08 13:25:31 +09002/*
3 * Copyright (C) 2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada2aa4b5b2016-10-08 13:25:31 +09005 */
6
7#include <common.h>
Simon Glass11c89f32017-05-17 17:18:03 -06008#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -06009#include <log.h>
Simon Glass9bc15642020-02-03 07:36:16 -070010#include <malloc.h>
Masahiro Yamada2aa4b5b2016-10-08 13:25:31 +090011#include <reset-uclass.h>
Simon Glass9bc15642020-02-03 07:36:16 -070012#include <dm/device_compat.h>
Masahiro Yamada2aa4b5b2016-10-08 13:25:31 +090013#include <linux/bitops.h>
14#include <linux/io.h>
15#include <linux/sizes.h>
16
17struct uniphier_reset_data {
18 unsigned int id;
19 unsigned int reg;
20 unsigned int bit;
21 unsigned int flags;
22#define UNIPHIER_RESET_ACTIVE_LOW BIT(0)
23};
24
25#define UNIPHIER_RESET_ID_END (unsigned int)(-1)
26
27#define UNIPHIER_RESET_END \
28 { .id = UNIPHIER_RESET_ID_END }
29
30#define UNIPHIER_RESET(_id, _reg, _bit) \
31 { \
32 .id = (_id), \
33 .reg = (_reg), \
34 .bit = (_bit), \
35 }
36
37#define UNIPHIER_RESETX(_id, _reg, _bit) \
38 { \
39 .id = (_id), \
40 .reg = (_reg), \
41 .bit = (_bit), \
42 .flags = UNIPHIER_RESET_ACTIVE_LOW, \
43 }
44
45/* System reset data */
Masahiro Yamada5e05c4d2017-06-22 16:42:04 +090046static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = {
Masahiro Yamada0eb2cec2017-08-13 09:01:16 +090047 UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
Kunihiko Hayashi6cce8372018-04-18 10:06:07 +090048 UNIPHIER_RESETX(6, 0x2000, 12), /* ETHER */
Masahiro Yamada0eb2cec2017-08-13 09:01:16 +090049 UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC */
50 UNIPHIER_RESETX(12, 0x2000, 6), /* GIO */
51 UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */
52 UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */
Masahiro Yamada2aa4b5b2016-10-08 13:25:31 +090053 UNIPHIER_RESET_END,
54};
55
Masahiro Yamada5e05c4d2017-06-22 16:42:04 +090056static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = {
Masahiro Yamada0eb2cec2017-08-13 09:01:16 +090057 UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
Kunihiko Hayashi6cce8372018-04-18 10:06:07 +090058 UNIPHIER_RESETX(6, 0x2000, 12), /* ETHER */
Masahiro Yamada0eb2cec2017-08-13 09:01:16 +090059 UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC */
60 UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */
61 UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */
Masahiro Yamada2aa4b5b2016-10-08 13:25:31 +090062 UNIPHIER_RESETX(16, 0x2014, 4), /* USB30-PHY0 */
63 UNIPHIER_RESETX(17, 0x2014, 0), /* USB30-PHY1 */
64 UNIPHIER_RESETX(18, 0x2014, 2), /* USB30-PHY2 */
65 UNIPHIER_RESETX(20, 0x2014, 5), /* USB31-PHY0 */
66 UNIPHIER_RESETX(21, 0x2014, 1), /* USB31-PHY1 */
67 UNIPHIER_RESETX(28, 0x2014, 12), /* SATA */
68 UNIPHIER_RESET(29, 0x2014, 8), /* SATA-PHY (active high) */
69 UNIPHIER_RESET_END,
70};
71
Masahiro Yamada5e05c4d2017-06-22 16:42:04 +090072static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = {
Masahiro Yamada0eb2cec2017-08-13 09:01:16 +090073 UNIPHIER_RESETX(2, 0x200c, 0), /* NAND */
74 UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */
Kunihiko Hayashi6cce8372018-04-18 10:06:07 +090075 UNIPHIER_RESETX(6, 0x200c, 6), /* ETHER */
Masahiro Yamada0eb2cec2017-08-13 09:01:16 +090076 UNIPHIER_RESETX(8, 0x200c, 8), /* STDMAC */
Masahiro Yamada096c4662018-06-19 16:11:43 +090077 UNIPHIER_RESETX(14, 0x200c, 5), /* USB30 */
Masahiro Yamada2aa4b5b2016-10-08 13:25:31 +090078 UNIPHIER_RESETX(16, 0x200c, 12), /* USB30-PHY0 */
79 UNIPHIER_RESETX(17, 0x200c, 13), /* USB30-PHY1 */
80 UNIPHIER_RESETX(18, 0x200c, 14), /* USB30-PHY2 */
81 UNIPHIER_RESETX(19, 0x200c, 15), /* USB30-PHY3 */
82 UNIPHIER_RESET_END,
83};
84
Masahiro Yamada8eb6a1c2017-08-29 12:20:51 +090085static const struct uniphier_reset_data uniphier_pxs3_sys_reset_data[] = {
86 UNIPHIER_RESETX(2, 0x200c, 0), /* NAND */
87 UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */
Kunihiko Hayashi6cce8372018-04-18 10:06:07 +090088 UNIPHIER_RESETX(6, 0x200c, 9), /* ETHER0 */
89 UNIPHIER_RESETX(7, 0x200c, 10), /* ETHER1 */
Masahiro Yamada8eb6a1c2017-08-29 12:20:51 +090090 UNIPHIER_RESETX(8, 0x200c, 12), /* STDMAC */
Masahiro Yamada096c4662018-06-19 16:11:43 +090091 UNIPHIER_RESETX(12, 0x200c, 4), /* USB30 link */
92 UNIPHIER_RESETX(13, 0x200c, 5), /* USB31 link */
93 UNIPHIER_RESETX(16, 0x200c, 16), /* USB30-PHY0 */
94 UNIPHIER_RESETX(17, 0x200c, 18), /* USB30-PHY1 */
95 UNIPHIER_RESETX(18, 0x200c, 20), /* USB30-PHY2 */
96 UNIPHIER_RESETX(20, 0x200c, 17), /* USB31-PHY0 */
97 UNIPHIER_RESETX(21, 0x200c, 19), /* USB31-PHY1 */
Masahiro Yamada8eb6a1c2017-08-29 12:20:51 +090098 UNIPHIER_RESET_END,
99};
100
Masahiro Yamada2aa4b5b2016-10-08 13:25:31 +0900101/* Media I/O reset data */
102#define UNIPHIER_MIO_RESET_SD(id, ch) \
103 UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 0)
104
105#define UNIPHIER_MIO_RESET_SD_BRIDGE(id, ch) \
106 UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 26)
107
108#define UNIPHIER_MIO_RESET_EMMC_HW_RESET(id, ch) \
109 UNIPHIER_RESETX((id), 0x80 + 0x200 * (ch), 0)
110
111#define UNIPHIER_MIO_RESET_USB2(id, ch) \
112 UNIPHIER_RESETX((id), 0x114 + 0x200 * (ch), 0)
113
114#define UNIPHIER_MIO_RESET_USB2_BRIDGE(id, ch) \
115 UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 24)
116
117#define UNIPHIER_MIO_RESET_DMAC(id) \
118 UNIPHIER_RESETX((id), 0x110, 17)
119
Masahiro Yamada5e05c4d2017-06-22 16:42:04 +0900120static const struct uniphier_reset_data uniphier_mio_reset_data[] = {
Masahiro Yamada2aa4b5b2016-10-08 13:25:31 +0900121 UNIPHIER_MIO_RESET_SD(0, 0),
122 UNIPHIER_MIO_RESET_SD(1, 1),
123 UNIPHIER_MIO_RESET_SD(2, 2),
124 UNIPHIER_MIO_RESET_SD_BRIDGE(3, 0),
125 UNIPHIER_MIO_RESET_SD_BRIDGE(4, 1),
126 UNIPHIER_MIO_RESET_SD_BRIDGE(5, 2),
127 UNIPHIER_MIO_RESET_EMMC_HW_RESET(6, 1),
128 UNIPHIER_MIO_RESET_DMAC(7),
129 UNIPHIER_MIO_RESET_USB2(8, 0),
130 UNIPHIER_MIO_RESET_USB2(9, 1),
131 UNIPHIER_MIO_RESET_USB2(10, 2),
132 UNIPHIER_MIO_RESET_USB2(11, 3),
133 UNIPHIER_MIO_RESET_USB2_BRIDGE(12, 0),
134 UNIPHIER_MIO_RESET_USB2_BRIDGE(13, 1),
135 UNIPHIER_MIO_RESET_USB2_BRIDGE(14, 2),
136 UNIPHIER_MIO_RESET_USB2_BRIDGE(15, 3),
137 UNIPHIER_RESET_END,
138};
139
140/* Peripheral reset data */
141#define UNIPHIER_PERI_RESET_UART(id, ch) \
142 UNIPHIER_RESETX((id), 0x114, 19 + (ch))
143
144#define UNIPHIER_PERI_RESET_I2C(id, ch) \
145 UNIPHIER_RESETX((id), 0x114, 5 + (ch))
146
147#define UNIPHIER_PERI_RESET_FI2C(id, ch) \
148 UNIPHIER_RESETX((id), 0x114, 24 + (ch))
149
Masahiro Yamada5e05c4d2017-06-22 16:42:04 +0900150static const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = {
Masahiro Yamada2aa4b5b2016-10-08 13:25:31 +0900151 UNIPHIER_PERI_RESET_UART(0, 0),
152 UNIPHIER_PERI_RESET_UART(1, 1),
153 UNIPHIER_PERI_RESET_UART(2, 2),
154 UNIPHIER_PERI_RESET_UART(3, 3),
155 UNIPHIER_PERI_RESET_I2C(4, 0),
156 UNIPHIER_PERI_RESET_I2C(5, 1),
157 UNIPHIER_PERI_RESET_I2C(6, 2),
158 UNIPHIER_PERI_RESET_I2C(7, 3),
159 UNIPHIER_PERI_RESET_I2C(8, 4),
160 UNIPHIER_RESET_END,
161};
162
Masahiro Yamada5e05c4d2017-06-22 16:42:04 +0900163static const struct uniphier_reset_data uniphier_pro4_peri_reset_data[] = {
Masahiro Yamada2aa4b5b2016-10-08 13:25:31 +0900164 UNIPHIER_PERI_RESET_UART(0, 0),
165 UNIPHIER_PERI_RESET_UART(1, 1),
166 UNIPHIER_PERI_RESET_UART(2, 2),
167 UNIPHIER_PERI_RESET_UART(3, 3),
168 UNIPHIER_PERI_RESET_FI2C(4, 0),
169 UNIPHIER_PERI_RESET_FI2C(5, 1),
170 UNIPHIER_PERI_RESET_FI2C(6, 2),
171 UNIPHIER_PERI_RESET_FI2C(7, 3),
172 UNIPHIER_PERI_RESET_FI2C(8, 4),
173 UNIPHIER_PERI_RESET_FI2C(9, 5),
174 UNIPHIER_PERI_RESET_FI2C(10, 6),
175 UNIPHIER_RESET_END,
176};
177
178/* core implementaton */
179struct uniphier_reset_priv {
180 void __iomem *base;
181 const struct uniphier_reset_data *data;
182};
183
184static int uniphier_reset_request(struct reset_ctl *reset_ctl)
185{
186 return 0;
187}
188
189static int uniphier_reset_free(struct reset_ctl *reset_ctl)
190{
191 return 0;
192}
193
194static int uniphier_reset_update(struct reset_ctl *reset_ctl, int assert)
195{
196 struct uniphier_reset_priv *priv = dev_get_priv(reset_ctl->dev);
197 unsigned long id = reset_ctl->id;
198 const struct uniphier_reset_data *p;
199
200 for (p = priv->data; p->id != UNIPHIER_RESET_ID_END; p++) {
201 u32 mask, val;
202
203 if (p->id != id)
204 continue;
205
206 val = readl(priv->base + p->reg);
207
208 if (p->flags & UNIPHIER_RESET_ACTIVE_LOW)
209 assert = !assert;
210
211 mask = BIT(p->bit);
212
213 if (assert)
214 val |= mask;
215 else
216 val &= ~mask;
217
218 writel(val, priv->base + p->reg);
219
220 return 0;
221 }
222
Masahiro Yamada63f42e32017-10-13 19:22:02 +0900223 dev_err(reset_ctl->dev, "reset_id=%lu was not handled\n", id);
224
Masahiro Yamada2aa4b5b2016-10-08 13:25:31 +0900225 return -EINVAL;
226}
227
228static int uniphier_reset_assert(struct reset_ctl *reset_ctl)
229{
230 return uniphier_reset_update(reset_ctl, 1);
231}
232
233static int uniphier_reset_deassert(struct reset_ctl *reset_ctl)
234{
235 return uniphier_reset_update(reset_ctl, 0);
236}
237
238static const struct reset_ops uniphier_reset_ops = {
239 .request = uniphier_reset_request,
Simon Glass1928cd42020-02-03 07:35:52 -0700240 .rfree = uniphier_reset_free,
Masahiro Yamada2aa4b5b2016-10-08 13:25:31 +0900241 .rst_assert = uniphier_reset_assert,
242 .rst_deassert = uniphier_reset_deassert,
243};
244
245static int uniphier_reset_probe(struct udevice *dev)
246{
247 struct uniphier_reset_priv *priv = dev_get_priv(dev);
248 fdt_addr_t addr;
249
Masahiro Yamadaa89b4de2020-07-17 14:36:48 +0900250 addr = dev_read_addr(dev->parent);
Masahiro Yamada2aa4b5b2016-10-08 13:25:31 +0900251 if (addr == FDT_ADDR_T_NONE)
252 return -EINVAL;
253
254 priv->base = devm_ioremap(dev, addr, SZ_4K);
255 if (!priv->base)
256 return -ENOMEM;
257
258 priv->data = (void *)dev_get_driver_data(dev);
259
260 return 0;
261}
262
263static const struct udevice_id uniphier_reset_match[] = {
264 /* System reset */
265 {
Masahiro Yamada2aa4b5b2016-10-08 13:25:31 +0900266 .compatible = "socionext,uniphier-ld4-reset",
Masahiro Yamada0eb2cec2017-08-13 09:01:16 +0900267 .data = (ulong)uniphier_pro4_sys_reset_data,
Masahiro Yamada2aa4b5b2016-10-08 13:25:31 +0900268 },
269 {
270 .compatible = "socionext,uniphier-pro4-reset",
271 .data = (ulong)uniphier_pro4_sys_reset_data,
272 },
273 {
274 .compatible = "socionext,uniphier-sld8-reset",
Masahiro Yamada0eb2cec2017-08-13 09:01:16 +0900275 .data = (ulong)uniphier_pro4_sys_reset_data,
Masahiro Yamada2aa4b5b2016-10-08 13:25:31 +0900276 },
277 {
278 .compatible = "socionext,uniphier-pro5-reset",
Masahiro Yamada0eb2cec2017-08-13 09:01:16 +0900279 .data = (ulong)uniphier_pro4_sys_reset_data,
Masahiro Yamada2aa4b5b2016-10-08 13:25:31 +0900280 },
281 {
282 .compatible = "socionext,uniphier-pxs2-reset",
283 .data = (ulong)uniphier_pxs2_sys_reset_data,
284 },
285 {
286 .compatible = "socionext,uniphier-ld11-reset",
Masahiro Yamada0eb2cec2017-08-13 09:01:16 +0900287 .data = (ulong)uniphier_ld20_sys_reset_data,
Masahiro Yamada2aa4b5b2016-10-08 13:25:31 +0900288 },
289 {
290 .compatible = "socionext,uniphier-ld20-reset",
291 .data = (ulong)uniphier_ld20_sys_reset_data,
292 },
Masahiro Yamada8eb6a1c2017-08-29 12:20:51 +0900293 {
294 .compatible = "socionext,uniphier-pxs3-reset",
295 .data = (ulong)uniphier_pxs3_sys_reset_data,
296 },
Masahiro Yamada2aa4b5b2016-10-08 13:25:31 +0900297 /* Media I/O reset */
298 {
Masahiro Yamada2aa4b5b2016-10-08 13:25:31 +0900299 .compatible = "socionext,uniphier-ld4-mio-reset",
300 .data = (ulong)uniphier_mio_reset_data,
301 },
302 {
303 .compatible = "socionext,uniphier-pro4-mio-reset",
304 .data = (ulong)uniphier_mio_reset_data,
305 },
306 {
307 .compatible = "socionext,uniphier-sld8-mio-reset",
308 .data = (ulong)uniphier_mio_reset_data,
309 },
310 {
311 .compatible = "socionext,uniphier-pro5-mio-reset",
312 .data = (ulong)uniphier_mio_reset_data,
313 },
314 {
315 .compatible = "socionext,uniphier-pxs2-mio-reset",
316 .data = (ulong)uniphier_mio_reset_data,
317 },
318 {
319 .compatible = "socionext,uniphier-ld11-mio-reset",
320 .data = (ulong)uniphier_mio_reset_data,
321 },
322 {
Masahiro Yamada68199a22017-08-29 12:20:50 +0900323 .compatible = "socionext,uniphier-ld11-sd-reset",
324 .data = (ulong)uniphier_mio_reset_data,
325 },
326 {
327 .compatible = "socionext,uniphier-ld20-sd-reset",
Masahiro Yamada2aa4b5b2016-10-08 13:25:31 +0900328 .data = (ulong)uniphier_mio_reset_data,
329 },
Masahiro Yamada8eb6a1c2017-08-29 12:20:51 +0900330 {
331 .compatible = "socionext,uniphier-pxs3-sd-reset",
332 .data = (ulong)uniphier_mio_reset_data,
333 },
Masahiro Yamada2aa4b5b2016-10-08 13:25:31 +0900334 /* Peripheral reset */
335 {
336 .compatible = "socionext,uniphier-ld4-peri-reset",
337 .data = (ulong)uniphier_ld4_peri_reset_data,
338 },
339 {
340 .compatible = "socionext,uniphier-pro4-peri-reset",
341 .data = (ulong)uniphier_pro4_peri_reset_data,
342 },
343 {
344 .compatible = "socionext,uniphier-sld8-peri-reset",
345 .data = (ulong)uniphier_ld4_peri_reset_data,
346 },
347 {
348 .compatible = "socionext,uniphier-pro5-peri-reset",
349 .data = (ulong)uniphier_pro4_peri_reset_data,
350 },
351 {
352 .compatible = "socionext,uniphier-pxs2-peri-reset",
353 .data = (ulong)uniphier_pro4_peri_reset_data,
354 },
355 {
356 .compatible = "socionext,uniphier-ld11-peri-reset",
357 .data = (ulong)uniphier_pro4_peri_reset_data,
358 },
359 {
360 .compatible = "socionext,uniphier-ld20-peri-reset",
361 .data = (ulong)uniphier_pro4_peri_reset_data,
362 },
Masahiro Yamada8eb6a1c2017-08-29 12:20:51 +0900363 {
364 .compatible = "socionext,uniphier-pxs3-peri-reset",
365 .data = (ulong)uniphier_pro4_peri_reset_data,
366 },
Masahiro Yamada2aa4b5b2016-10-08 13:25:31 +0900367 { /* sentinel */ }
368};
369
370U_BOOT_DRIVER(uniphier_reset) = {
371 .name = "uniphier-reset",
372 .id = UCLASS_RESET,
373 .of_match = uniphier_reset_match,
374 .probe = uniphier_reset_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700375 .priv_auto = sizeof(struct uniphier_reset_priv),
Masahiro Yamada2aa4b5b2016-10-08 13:25:31 +0900376 .ops = &uniphier_reset_ops,
377};