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git01.mediatek.com / filogic / uboot / 43d9972b2bed73657085400d6e9a3e3fde27e6fa / . / drivers / ufs / cdns-platform.c
blob: 1a7bb7bed8a777803bdbb26f862e3ae7ba82de70 [file] [log] [blame]
Faiz Abbas204b2c22019-10-15 18:24:37 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/**
3 * cdns-platform.c - Platform driver for Cadence UFSHCI device
4 *
5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
6 */
7
8#include <clk.h>
9#include <common.h>
10#include <dm.h>
11#include <ufs.h>
Simon Glass9bc15642020-02-03 07:36:16 -0700[diff] [blame]12#include <dm/device_compat.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -0600[diff] [blame]13#include <linux/bitops.h>
Simon Glassd66c5f72020-02-03 07:36:15 -0700[diff] [blame]14#include <linux/err.h>
Faiz Abbas204b2c22019-10-15 18:24:37 +0530[diff] [blame]15
16#include "ufs.h"
17
18#define USEC_PER_SEC 1000000L
19
20#define CDNS_UFS_REG_HCLKDIV 0xFC
21#define CDNS_UFS_REG_PHY_XCFGD1 0x113C
22
23static int cdns_ufs_link_startup_notify(struct ufs_hba *hba,
24 enum ufs_notify_change_status status)
25{
26 hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC;
27 switch (status) {
28 case PRE_CHANGE:
29 return ufshcd_dme_set(hba,
30 UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE),
31 0);
32 case POST_CHANGE:
33 ;
34 }
35
36 return 0;
37}
38
39static int cdns_ufs_set_hclkdiv(struct ufs_hba *hba)
40{
41 struct clk clk;
42 unsigned long core_clk_rate = 0;
43 u32 core_clk_div = 0;
44 int ret;
45
46 ret = clk_get_by_name(hba->dev, "core_clk", &clk);
47 if (ret) {
48 dev_err(hba->dev, "failed to get core_clk clock\n");
49 return ret;
50 }
51
52 core_clk_rate = clk_get_rate(&clk);
53 if (IS_ERR_VALUE(core_clk_rate)) {
54 dev_err(hba->dev, "%s: unable to find core_clk rate\n",
55 __func__);
56 return core_clk_rate;
57 }
58
59 core_clk_div = core_clk_rate / USEC_PER_SEC;
60 ufshcd_writel(hba, core_clk_div, CDNS_UFS_REG_HCLKDIV);
61
62 return 0;
63}
64
65static int cdns_ufs_hce_enable_notify(struct ufs_hba *hba,
66 enum ufs_notify_change_status status)
67{
68 switch (status) {
69 case PRE_CHANGE:
70 return cdns_ufs_set_hclkdiv(hba);
71 case POST_CHANGE:
72 ;
73 }
74
75 return 0;
76}
77
78static int cdns_ufs_init(struct ufs_hba *hba)
79{
80 u32 data;
81
82 /* Increase RX_Advanced_Min_ActivateTime_Capability */
83 data = ufshcd_readl(hba, CDNS_UFS_REG_PHY_XCFGD1);
84 data |= BIT(24);
85 ufshcd_writel(hba, data, CDNS_UFS_REG_PHY_XCFGD1);
86
87 return 0;
88}
89
90static struct ufs_hba_ops cdns_pltfm_hba_ops = {
91 .init = cdns_ufs_init,
92 .hce_enable_notify = cdns_ufs_hce_enable_notify,
93 .link_startup_notify = cdns_ufs_link_startup_notify,
94};
95
96static int cdns_ufs_pltfm_probe(struct udevice *dev)
97{
98 int err = ufshcd_probe(dev, &cdns_pltfm_hba_ops);
99 if (err)
100 dev_err(dev, "ufshcd_probe() failed %d\n", err);
101
102 return err;
103}
104
105static int cdns_ufs_pltfm_bind(struct udevice *dev)
106{
107 struct udevice *scsi_dev;
108
109 return ufs_scsi_bind(dev, &scsi_dev);
110}
111
112static const struct udevice_id cdns_ufs_pltfm_ids[] = {
113 {
114 .compatible = "cdns,ufshc-m31-16nm",
115 },
116 {},
117};
118
119U_BOOT_DRIVER(cdns_ufs_pltfm) = {
120 .name = "cdns-ufs-pltfm",
121 .id = UCLASS_UFS,
122 .of_match = cdns_ufs_pltfm_ids,
123 .probe = cdns_ufs_pltfm_probe,
124 .bind = cdns_ufs_pltfm_bind,
125};