blob: 04b23085f83603dac459134daba8786c794cbe46 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Priyanka Jain8b1a60e2013-10-18 17:19:06 +05302/*
3 * Copyright 2013 Freescale Semiconductor, Inc.
Priyanka Jain8b1a60e2013-10-18 17:19:06 +05304 */
5
6#include <common.h>
7#include <command.h>
Simon Glass0af6e2d2019-08-01 09:46:52 -06008#include <env.h>
Simon Glass3bbe70c2019-12-28 10:44:54 -07009#include <fdt_support.h>
Zhao Qiang81136a12015-08-28 10:31:50 +080010#include <hwconfig.h>
Simon Glass2dc9c342020-05-10 11:40:01 -060011#include <image.h>
Simon Glassa7b51302019-11-14 12:57:46 -070012#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060013#include <log.h>
Priyanka Jain8b1a60e2013-10-18 17:19:06 +053014#include <netdev.h>
15#include <linux/compiler.h>
16#include <asm/mmu.h>
17#include <asm/processor.h>
18#include <asm/cache.h>
19#include <asm/immap_85xx.h>
Zhao Qiang81136a12015-08-28 10:31:50 +080020#include <asm/fsl_fdt.h>
Priyanka Jain8b1a60e2013-10-18 17:19:06 +053021#include <asm/fsl_law.h>
22#include <asm/fsl_serdes.h>
Priyanka Jain8b1a60e2013-10-18 17:19:06 +053023#include <asm/fsl_liodn.h>
24#include <fm_eth.h>
Tang Yuantian760eafc2014-11-21 11:17:16 +080025#include "../common/sleep.h"
Priyanka Jain8b1a60e2013-10-18 17:19:06 +053026#include "t104xrdb.h"
Prabhakar Kushwahae5e66332014-04-03 16:50:05 +053027#include "cpld.h"
Priyanka Jain8b1a60e2013-10-18 17:19:06 +053028
29DECLARE_GLOBAL_DATA_PTR;
30
31int checkboard(void)
32{
33 struct cpu_type *cpu = gd->arch.cpu;
Prabhakar Kushwahae5e66332014-04-03 16:50:05 +053034 u8 sw;
Priyanka Jain8b1a60e2013-10-18 17:19:06 +053035
York Sun097aa602016-11-21 11:25:26 -080036#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
Priyanka Jaine7597fe2015-06-05 15:29:02 +053037 printf("Board: %sD4RDB\n", cpu->name);
38#else
Priyanka Jain8b1a60e2013-10-18 17:19:06 +053039 printf("Board: %sRDB\n", cpu->name);
Priyanka Jaine7597fe2015-06-05 15:29:02 +053040#endif
Prabhakar Kushwahae5e66332014-04-03 16:50:05 +053041 printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
42 CPLD_READ(hw_ver), CPLD_READ(sw_ver));
43
44 sw = CPLD_READ(flash_ctl_status);
45 sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
46
Priyanka Jain86c6bfe2015-07-30 10:20:18 +053047 printf("vBank: %d\n", sw);
Prabhakar Kushwahae5e66332014-04-03 16:50:05 +053048
Priyanka Jain8b1a60e2013-10-18 17:19:06 +053049 return 0;
50}
51
Tang Yuantian760eafc2014-11-21 11:17:16 +080052int board_early_init_f(void)
53{
54#if defined(CONFIG_DEEP_SLEEP)
55 if (is_warm_boot())
56 fsl_dp_disable_console();
57#endif
58
59 return 0;
60}
61
Priyanka Jain8b1a60e2013-10-18 17:19:06 +053062int board_early_init_r(void)
63{
64#ifdef CONFIG_SYS_FLASH_BASE
65 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
York Sun220c3462014-06-24 21:16:20 -070066 int flash_esel = find_tlb_idx((void *)flashbase, 1);
Priyanka Jain8b1a60e2013-10-18 17:19:06 +053067
68 /*
69 * Remap Boot flash region to caching-inhibited
70 * so that flash can be erased properly.
71 */
72
73 /* Flush d-cache and invalidate i-cache of any FLASH data */
74 flush_dcache();
75 invalidate_icache();
76
York Sun220c3462014-06-24 21:16:20 -070077 if (flash_esel == -1) {
78 /* very unlikely unless something is messed up */
79 puts("Error: Could not find TLB for FLASH BASE\n");
80 flash_esel = 2; /* give our best effort to continue */
81 } else {
82 /* invalidate existing TLB entry for flash */
83 disable_tlb(flash_esel);
84 }
Priyanka Jain8b1a60e2013-10-18 17:19:06 +053085
86 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
87 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
88 0, flash_esel, BOOKE_PAGESZ_256M, 1);
89#endif
Priyanka Jain8b1a60e2013-10-18 17:19:06 +053090 return 0;
91}
92
93int misc_init_r(void)
94{
Priyanka Jaine7597fe2015-06-05 15:29:02 +053095 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
96 u32 srds_s1;
97
98 srds_s1 = in_be32(&gur->rcwsr[4]) >> 24;
99
100 printf("SERDES Reference : 0x%X\n", srds_s1);
101
102 /* select SGMII*/
103 if (srds_s1 == 0x86)
104 CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
105 MISC_CTL_SG_SEL);
106
107 /* select SGMII and Aurora*/
108 if (srds_s1 == 0x8E)
109 CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
110 MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL);
111
York Sun2c156012016-11-21 10:46:53 -0800112#if defined(CONFIG_TARGET_T1040D4RDB)
Zhao Qiang81136a12015-08-28 10:31:50 +0800113 if (hwconfig("qe-tdm")) {
114 CPLD_WRITE(sfp_ctl_status, CPLD_READ(sfp_ctl_status) |
115 MISC_MUX_QE_TDM);
116 printf("QECSR : 0x%02x, mux to qe-tdm\n",
117 CPLD_READ(sfp_ctl_status));
118 }
Priyanka Jaine7597fe2015-06-05 15:29:02 +0530119 /* Mask all CPLD interrupt sources, except QSGMII interrupts */
120 if (CPLD_READ(sw_ver) < 0x03) {
121 debug("CPLD SW version 0x%02x doesn't support int_mask\n",
122 CPLD_READ(sw_ver));
123 } else {
124 CPLD_WRITE(int_mask, CPLD_INT_MASK_ALL &
125 ~(CPLD_INT_MASK_QSGMII1 | CPLD_INT_MASK_QSGMII2));
126 }
127#endif
128
Priyanka Jain8b1a60e2013-10-18 17:19:06 +0530129 return 0;
130}
131
Simon Glass2aec3cc2014-10-23 18:58:47 -0600132int ft_board_setup(void *blob, bd_t *bd)
Priyanka Jain8b1a60e2013-10-18 17:19:06 +0530133{
134 phys_addr_t base;
135 phys_size_t size;
136
137 ft_cpu_setup(blob, bd);
138
Simon Glassda1a1342017-08-03 12:22:15 -0600139 base = env_get_bootm_low();
140 size = env_get_bootm_size();
Priyanka Jain8b1a60e2013-10-18 17:19:06 +0530141
142 fdt_fixup_memory(blob, (u64)base, (u64)size);
143
144#ifdef CONFIG_PCI
145 pci_of_setup(blob, bd);
146#endif
147
148 fdt_fixup_liodn(blob);
149
150#ifdef CONFIG_HAS_FSL_DR_USB
Sriram Dash9fd465c2016-09-16 17:12:15 +0530151 fsl_fdt_fixup_dr_usb(blob, bd);
Priyanka Jain8b1a60e2013-10-18 17:19:06 +0530152#endif
153
154#ifdef CONFIG_SYS_DPAA_FMAN
Madalin Bucur70848512020-04-30 15:59:58 +0300155#ifndef CONFIG_DM_ETH
Priyanka Jain8b1a60e2013-10-18 17:19:06 +0530156 fdt_fixup_fman_ethernet(blob);
157#endif
Madalin Bucur70848512020-04-30 15:59:58 +0300158#endif
Simon Glass2aec3cc2014-10-23 18:58:47 -0600159
Zhao Qiang81136a12015-08-28 10:31:50 +0800160 if (hwconfig("qe-tdm"))
161 fdt_del_diu(blob);
Simon Glass2aec3cc2014-10-23 18:58:47 -0600162 return 0;
Priyanka Jain8b1a60e2013-10-18 17:19:06 +0530163}