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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -05002/*
3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
Alison Wang8d8dac92012-03-26 21:49:08 +00006 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -05007 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -05008 */
9
10#include <common.h>
Simon Glass18afe102019-11-14 12:57:47 -070011#include <init.h>
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -050012#include <pci.h>
13#include <asm/immap.h>
Alison Wang8d8dac92012-03-26 21:49:08 +000014#include <asm/io.h>
Simon Glassdbd79542020-05-10 11:40:11 -060015#include <linux/delay.h>
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -050016
17DECLARE_GLOBAL_DATA_PTR;
18
19int checkboard(void)
20{
21 puts("Board: ");
22 puts("Freescale M54455 EVB\n");
23 return 0;
24};
25
Simon Glassd35f3382017-04-06 12:47:05 -060026int dram_init(void)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -050027{
TsiChung Liew23cf8fd2008-07-23 20:38:53 -050028 u32 dramsize;
29#ifdef CONFIG_CF_SBF
30 /*
31 * Serial Boot: The dram is already initialized in start.S
32 * only require to return DRAM size
33 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020034 dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
TsiChung Liew23cf8fd2008-07-23 20:38:53 -050035#else
Alison Wang8d8dac92012-03-26 21:49:08 +000036 sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
37 gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
TsiChung Liew23cf8fd2008-07-23 20:38:53 -050038 u32 i;
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -050039
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020040 dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -050041
42 for (i = 0x13; i < 0x20; i++) {
43 if (dramsize == (1 << i))
44 break;
45 }
46 i--;
47
Alison Wang8d8dac92012-03-26 21:49:08 +000048 out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -050049
Alison Wang8d8dac92012-03-26 21:49:08 +000050 out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
51 out_be32(&sdram->sdcs1, CONFIG_SYS_SDRAM_BASE1 | i);
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -050052
Alison Wang8d8dac92012-03-26 21:49:08 +000053 out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
54 out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -050055
56 /* Issue PALL */
Alison Wang8d8dac92012-03-26 21:49:08 +000057 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -050058
59 /* Issue LEMR */
Alison Wang8d8dac92012-03-26 21:49:08 +000060 out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD | 0x408);
61 out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x300);
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -050062
63 udelay(500);
64
65 /* Issue PALL */
Alison Wang8d8dac92012-03-26 21:49:08 +000066 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -050067
68 /* Perform two refresh cycles */
Alison Wang8d8dac92012-03-26 21:49:08 +000069 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
70 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -050071
Alison Wang8d8dac92012-03-26 21:49:08 +000072 out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x200);
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -050073
Alison Wang8d8dac92012-03-26 21:49:08 +000074 out_be32(&sdram->sdcr,
75 (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -050076
77 udelay(100);
TsiChung Liew23cf8fd2008-07-23 20:38:53 -050078#endif
Simon Glass39f90ba2017-03-31 08:40:25 -060079 gd->ram_size = dramsize << 1;
80
81 return 0;
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -050082};
83
84int testdram(void)
85{
86 /* TODO: XXX XXX XXX */
87 printf("DRAM test not implemented!\n");
88
89 return (0);
90}
91
Simon Glassb569a012017-05-17 03:25:30 -060092#if defined(CONFIG_IDE)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -050093#include <ata.h>
94
95int ide_preinit(void)
96{
Alison Wang8d8dac92012-03-26 21:49:08 +000097 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
98 u32 tmp;
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -050099
Alison Wang8d8dac92012-03-26 21:49:08 +0000100 tmp = (in_8(&gpio->par_fec) & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10;
101 setbits_8(&gpio->par_fec, tmp);
102 tmp = ((in_be16(&gpio->par_feci2c) & 0xf0ff) |
103 (GPIO_PAR_FECI2C_MDC1_ATA_DIOR | GPIO_PAR_FECI2C_MDIO1_ATA_DIOW));
104 setbits_be16(&gpio->par_feci2c, tmp);
105
106 setbits_be16(&gpio->par_ata,
107 GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 |
108 GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0 |
109 GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ |
110 GPIO_PAR_ATA_IORDY_IORDY);
111 setbits_be16(&gpio->par_pci,
112 GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ);
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500113
114 return (0);
115}
116
117void ide_set_reset(int idereset)
118{
Alison Wang8d8dac92012-03-26 21:49:08 +0000119 atac_t *ata = (atac_t *) MMAP_ATA;
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500120 long period;
121 /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
122 int piotms[5][9] = {
123 {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
124 {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */
125 {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */
126 {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */
127 {25, 70, 20, 10, 20, 5, 10, 0, 35}
128 }; /* PIO 4 */
129
130 if (idereset) {
Alison Wang8d8dac92012-03-26 21:49:08 +0000131 /* control reset */
132 out_8(&ata->cr, 0);
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500133 udelay(10000);
134 } else {
135#define CALC_TIMING(t) (t + period - 1) / period
136 period = 1000000000 / gd->bus_clk; /* period in ns */
137
138 /*ata->ton = CALC_TIMING (180); */
Alison Wang8d8dac92012-03-26 21:49:08 +0000139 out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
140 out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
141 out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
142 out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
143 out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
144 out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
145 out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500146
Alison Wang8d8dac92012-03-26 21:49:08 +0000147 /* IORDY enable */
148 out_8(&ata->cr, 0x40);
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500149 udelay(200000);
Alison Wang8d8dac92012-03-26 21:49:08 +0000150 /* IORDY enable */
151 setbits_8(&ata->cr, 0x01);
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500152 }
153}
154#endif
155
156#if defined(CONFIG_PCI)
157/*
158 * Initialize PCI devices, report devices found.
159 */
160static struct pci_controller hose;
161extern void pci_mcf5445x_init(struct pci_controller *hose);
162
163void pci_init_board(void)
164{
165 pci_mcf5445x_init(&hose);
166}
167#endif /* CONFIG_PCI */
TsiChung Liew77551092008-07-23 17:37:10 -0500168
TsiChung Liew56e622b2008-08-19 00:26:25 +0600169#if defined(CONFIG_FLASH_CFI_LEGACY)
TsiChung Liew77551092008-07-23 17:37:10 -0500170#include <flash.h>
171ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
172{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200173 int sect[] = CONFIG_SYS_ATMEL_SECT;
174 int sectsz[] = CONFIG_SYS_ATMEL_SECTSZ;
TsiChung Liew77551092008-07-23 17:37:10 -0500175 int i, j, k;
176
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200177 if (base != CONFIG_SYS_ATMEL_BASE)
TsiChung Liew77551092008-07-23 17:37:10 -0500178 return 0;
179
180 info->flash_id = 0x01000000;
181 info->portwidth = 1;
182 info->chipwidth = 1;
TsiChung Liew1f3a9382010-03-16 12:39:36 -0500183 info->buffer_size = 1;
TsiChung Liew77551092008-07-23 17:37:10 -0500184 info->erase_blk_tout = 16384;
185 info->write_tout = 2;
186 info->buffer_write_tout = 5;
TsiChung Liew56e622b2008-08-19 00:26:25 +0600187 info->vendor = 0xFFF0; /* CFI_CMDSET_AMD_LEGACY */
TsiChung Liew77551092008-07-23 17:37:10 -0500188 info->cmd_reset = 0x00F0;
189 info->interface = FLASH_CFI_X8;
190 info->legacy_unlock = 0;
191 info->manufacturer_id = (u16) ATM_MANUFACT;
192 info->device_id = ATM_ID_LV040;
193 info->device_id2 = 0;
194
195 info->ext_addr = 0;
196 info->cfi_version = 0x3133;
TsiChung Liew56e622b2008-08-19 00:26:25 +0600197 info->cfi_offset = 0x0000;
TsiChung Liew77551092008-07-23 17:37:10 -0500198 info->addr_unlock1 = 0x00000555;
199 info->addr_unlock2 = 0x000002AA;
200 info->name = "CFI conformant";
201
TsiChung Liew77551092008-07-23 17:37:10 -0500202 info->size = 0;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200203 info->sector_count = CONFIG_SYS_ATMEL_TOTALSECT;
TsiChung Liew77551092008-07-23 17:37:10 -0500204 info->start[0] = base;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200205 for (k = 0, i = 0; i < CONFIG_SYS_ATMEL_REGION; i++) {
TsiChung Liew77551092008-07-23 17:37:10 -0500206 info->size += sect[i] * sectsz[i];
207
208 for (j = 0; j < sect[i]; j++, k++) {
209 info->start[k + 1] = info->start[k] + sectsz[i];
210 info->protect[k] = 0;
211 }
212 }
213
214 return 1;
215}
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200216#endif /* CONFIG_SYS_FLASH_CFI */