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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Chris Zankel1387dab2016-08-10 18:36:44 +03002/*
3 * Miscellaneous assembly functions.
4 *
5 * Copyright (C) 2001 - 2007 Tensilica Inc.
6 * Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
7 *
8 * Chris Zankel <chris@zankel.net>
Chris Zankel1387dab2016-08-10 18:36:44 +03009 */
10
11
12#include <linux/linkage.h>
13#include <asm/asmmacro.h>
14#include <asm/cacheasm.h>
15
16/*
17 * void __invalidate_icache_page(ulong start)
18 */
19
20ENTRY(__invalidate_icache_page)
21
22 abi_entry
23
24 ___invalidate_icache_page a2 a3
25 isync
26
27 abi_ret
28
29ENDPROC(__invalidate_icache_page)
30
31/*
32 * void __invalidate_dcache_page(ulong start)
33 */
34
35ENTRY(__invalidate_dcache_page)
36
37 abi_entry
38
39 ___invalidate_dcache_page a2 a3
40 dsync
41
42 abi_ret
43
44ENDPROC(__invalidate_dcache_page)
45
46/*
47 * void __flush_invalidate_dcache_page(ulong start)
48 */
49
50ENTRY(__flush_invalidate_dcache_page)
51
52 abi_entry
53
54 ___flush_invalidate_dcache_page a2 a3
55
56 dsync
57 abi_ret
58
59ENDPROC(__flush_invalidate_dcache_page)
60
61/*
62 * void __flush_dcache_page(ulong start)
63 */
64
65ENTRY(__flush_dcache_page)
66
67 abi_entry
68
69 ___flush_dcache_page a2 a3
70
71 dsync
72 abi_ret
73
74ENDPROC(__flush_dcache_page)
75
76/*
77 * void __invalidate_icache_range(ulong start, ulong size)
78 */
79
80ENTRY(__invalidate_icache_range)
81
82 abi_entry
83
84 ___invalidate_icache_range a2 a3 a4
85 isync
86
87 abi_ret
88
89ENDPROC(__invalidate_icache_range)
90
91/*
92 * void __flush_invalidate_dcache_range(ulong start, ulong size)
93 */
94
95ENTRY(__flush_invalidate_dcache_range)
96
97 abi_entry
98
99 ___flush_invalidate_dcache_range a2 a3 a4
100 dsync
101
102 abi_ret
103
104ENDPROC(__flush_invalidate_dcache_range)
105
106/*
107 * void _flush_dcache_range(ulong start, ulong size)
108 */
109
110ENTRY(__flush_dcache_range)
111
112 abi_entry
113
114 ___flush_dcache_range a2 a3 a4
115 dsync
116
117 abi_ret
118
119ENDPROC(__flush_dcache_range)
120
121/*
122 * void _invalidate_dcache_range(ulong start, ulong size)
123 */
124
125ENTRY(__invalidate_dcache_range)
126
127 abi_entry
128
129 ___invalidate_dcache_range a2 a3 a4
130
131 abi_ret
132
133ENDPROC(__invalidate_dcache_range)
134
135/*
136 * void _invalidate_icache_all(void)
137 */
138
139ENTRY(__invalidate_icache_all)
140
141 abi_entry
142
143 ___invalidate_icache_all a2 a3
144 isync
145
146 abi_ret
147
148ENDPROC(__invalidate_icache_all)
149
150/*
151 * void _flush_invalidate_dcache_all(void)
152 */
153
154ENTRY(__flush_invalidate_dcache_all)
155
156 abi_entry
157
158 ___flush_invalidate_dcache_all a2 a3
159 dsync
160
161 abi_ret
162
163ENDPROC(__flush_invalidate_dcache_all)
164
165/*
166 * void _invalidate_dcache_all(void)
167 */
168
169ENTRY(__invalidate_dcache_all)
170
171 abi_entry
172
173 ___invalidate_dcache_all a2 a3
174 dsync
175
176 abi_ret
177
178ENDPROC(__invalidate_dcache_all)