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TsiChungLiewfc3ca3b62007-08-16 15:05:11 -05001/*
2 *
3 * (C) Copyright 2000-2004
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
Alison Wang8d8dac92012-03-26 21:49:08 +00006 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -05007 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28/* CPU specific interrupt routine */
29#include <common.h>
30#include <asm/immap.h>
Alison Wang8d8dac92012-03-26 21:49:08 +000031#include <asm/io.h>
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -050032
33int interrupt_init(void)
34{
Alison Wang8d8dac92012-03-26 21:49:08 +000035 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -050036
37 /* Make sure all interrupts are disabled */
Alison Wang8d8dac92012-03-26 21:49:08 +000038 setbits_be32(&intp->imrh0, 0xffffffff);
39 setbits_be32(&intp->imrl0, 0xffffffff);
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -050040
41 enable_interrupts();
42 return 0;
43}
44
45#if defined(CONFIG_MCFTMR)
46void dtimer_intr_setup(void)
47{
Alison Wang8d8dac92012-03-26 21:49:08 +000048 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -050049
Alison Wang8d8dac92012-03-26 21:49:08 +000050 out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
51 clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK);
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -050052}
53#endif