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git01.mediatek.com / filogic / uboot / 439a6ca80e770e47d7cf742c10796bd5796f81c0 / . / arch / arm / dts / rk3399-evb-u-boot.dtsi
blob: 9df4a02c3e740f6938f517b8e262e0c924a0115b [file] [log] [blame]
Jagan Teki112f6362019-05-07 23:51:50 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
4 */
5
Jagan Teki46dbd402019-05-07 23:51:52 +0530[diff] [blame]6#include "rk3399-u-boot.dtsi"
Jagan Teki112f6362019-05-07 23:51:50 +0530[diff] [blame]7#include "rk3399-sdram-lpddr3-4GB-1600.dtsi"
Peter Robinson68b13a02019-11-09 20:30:06 +0000[diff] [blame]8
9/ {
10 chosen {
Kever Yang5e12b102020-06-03 15:25:28 +0800[diff] [blame]11 stdout-path = "serial2:1500000n8";
Peter Robinson68b13a02019-11-09 20:30:06 +0000[diff] [blame]12 };
13};
Lin Jinhan3e714cf2020-03-31 17:39:57 +0800[diff] [blame]14
Jagan Teki5a1d0ac2020-04-28 15:30:15 +0530[diff] [blame]15&i2c0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]16 bootph-all;
Jagan Teki5a1d0ac2020-04-28 15:30:15 +0530[diff] [blame]17};
18
19&rk808 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]20 bootph-all;
Jagan Teki5a1d0ac2020-04-28 15:30:15 +0530[diff] [blame]21};
Frank Wangbeaa1392020-05-26 11:34:33 +0800[diff] [blame]22
23&tcphy1 {
24 status = "okay";
25};
26
27&usbdrd3_1 {
28 status = "okay";
29};
30
31&usbdrd_dwc3_1 {
32 dr_mode = "host";
33 status = "okay";
34};
Kever Yang0d590072020-08-11 14:44:30 +0800[diff] [blame]35
Kever Yang6185c812020-12-07 10:52:51 +0800[diff] [blame]36&vdd_center {
37 regulator-init-microvolt = <900000>;
38};
39
Kever Yang0d590072020-08-11 14:44:30 +0800[diff] [blame]40&sdmmc {
Kever Yang0d590072020-08-11 14:44:30 +0800[diff] [blame]41 bus-width = <4>;
42 cap-mmc-highspeed;
43 cap-sd-highspeed;
44 cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
45 disable-wp;
46 max-frequency = <150000000>;
47 pinctrl-names = "default";
48 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
49 status = "okay";
50};