Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 43936fd5592d2035d699d415aa55c9a1ea0bae73 / . / configs / ds414_defconfig
blob: 7af7bb4e980e1fab9753edf6660efb3de563d6f9 [file] [log] [blame]
Phil Sutterd76eba62015-12-25 14:41:25 +0100[diff] [blame]1CONFIG_ARM=y
Adam Fordd36b1022019-08-14 08:29:25 -0500[diff] [blame]2CONFIG_ARCH_CPU_INIT=y
Phil Sutterd76eba62015-12-25 14:41:25 +0100[diff] [blame]3CONFIG_ARCH_MVEBU=y
Tom Rini4cc38852021-08-30 09:16:30 -0400[diff] [blame]4CONFIG_SUPPORT_PASSING_ATAGS=y
5CONFIG_CMDLINE_TAG=y
6CONFIG_INITRD_TAG=y
Tom Riniea1e52b2021-08-30 09:16:31 -0400[diff] [blame]7CONFIG_STATIC_MACH_TYPE=y
8CONFIG_MACH_TYPE=3036
Tom Rini07edfae2018-02-03 12:10:38 -0500[diff] [blame]9CONFIG_SYS_TEXT_BASE=0x00800000
Simon Glassf2a89462016-09-12 23:18:41 -0600[diff] [blame]10CONFIG_SPL_LIBCOMMON_SUPPORT=y
Simon Glassb16c92c2016-09-12 23:18:43 -0600[diff] [blame]11CONFIG_SPL_LIBGENERIC_SUPPORT=y
Tom Rini2e262c42020-08-10 15:31:07 -0400[diff] [blame]12CONFIG_NR_DRAM_BANKS=2
Phil Sutterd76eba62015-12-25 14:41:25 +0100[diff] [blame]13CONFIG_TARGET_DS414=y
Tom Rini59180392021-08-21 13:50:13 -0400[diff] [blame]14CONFIG_DDR_32BIT=y
Tom Rini5cd7ece2019-11-18 20:02:10 -0500[diff] [blame]15CONFIG_ENV_SIZE=0x10000
16CONFIG_ENV_OFFSET=0x7E0000
Tom Rini47dece32020-04-28 16:15:47 -0400[diff] [blame]17CONFIG_ENV_SECT_SIZE=0x10000
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]18CONFIG_DEFAULT_DEVICE_TREE="armada-xp-synology-ds414"
Tom Rini0332a1a2020-07-06 13:54:25 -0400[diff] [blame]19CONFIG_SPL_TEXT_BASE=0x40004030
Simon Glassf4d60392021-08-08 12:20:12 -0600[diff] [blame]20CONFIG_SPL_SERIAL=y
Tom Rinie0056d72018-06-04 11:57:37 -0400[diff] [blame]21CONFIG_SPL=y
Pali Rohár40954732022-05-09 20:17:07 +0200[diff] [blame]22CONFIG_DEBUG_UART_BASE=0xf1012000
Tom Rinie0056d72018-06-04 11:57:37 -0400[diff] [blame]23CONFIG_DEBUG_UART_CLOCK=250000000
Tom Rini0997ee02021-08-23 10:25:31 -0400[diff] [blame]24CONFIG_SYS_LOAD_ADDR=0x800000
Tom Rini4b2fcb32022-04-08 13:36:51 -0400[diff] [blame]25CONFIG_DEBUG_UART=y
Tom Rini4ddbade2022-05-25 12:16:03 -0400[diff] [blame]26CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
27CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000
Heiko Schocher0b368b12016-06-07 08:31:14 +0200[diff] [blame]28CONFIG_BOOTDELAY=3
Sam Protsenkobd7bffe2017-08-14 20:22:17 +0300[diff] [blame]29CONFIG_USE_BOOTARGS=y
Phil Sutteref534b22021-03-07 22:22:27 +0100[diff] [blame]30CONFIG_BOOTARGS="console=ttyS0,115200 ip=off initrd=0x8000040,8M root=/dev/md0 rw syno_hw_version=DS414r1 ihd_num=4 netif_num=2 flash_size=8 SataLedSpecial=1 HddHotplug=1"
Tom Rini5ddf1722021-11-10 09:11:40 -0500[diff] [blame]31CONFIG_USE_BOOTCOMMAND=y
32CONFIG_BOOTCOMMAND="sf probe; sf read ${loadaddr} 0xd0000 0x2d0000; sf read ${ramdisk_addr_r} 0x3a0000 0x430000; bootm ${loadaddr} ${ramdisk_addr_r}"
Lokesh Vutla94d95e42016-10-11 21:33:46 -0400[diff] [blame]33# CONFIG_DISPLAY_BOARDINFO is not set
Mario Sixf7055442018-03-28 14:38:17 +0200[diff] [blame]34CONFIG_DISPLAY_BOARDINFO_LATE=y
Phil Suttere91d6882021-03-05 21:05:11 +0100[diff] [blame]35CONFIG_MISC_INIT_R=y
Tom Riniabb0f522022-05-16 17:20:26 -0400[diff] [blame]36CONFIG_SPL_MAX_SIZE=0x1bfd0
Tom Rini65aa1242022-05-27 10:19:45 -0400[diff] [blame]37CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
38CONFIG_SPL_BSS_START_ADDR=0x40020000
Tom Rini0cb89e72022-05-19 15:09:22 -0400[diff] [blame]39CONFIG_SPL_BSS_MAX_SIZE=0x4000
Tom Rinie7d67a42022-05-20 12:36:05 -0400[diff] [blame]40CONFIG_SPL_SYS_MALLOC_SIMPLE=y
Tom Rini8a14ac42022-05-26 13:13:21 -0400[diff] [blame]41# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
42CONFIG_SPL_STACK=0x4002c000
Simon Glassbccfc2e2021-07-10 21:14:36 -0600[diff] [blame]43CONFIG_SPL_I2C=y
Tom Riniba5c2b02022-05-11 16:21:06 -0400[diff] [blame]44CONFIG_SYS_MAXARGS=32
Phil Sutterd76eba62015-12-25 14:41:25 +0100[diff] [blame]45# CONFIG_CMD_FLASH is not set
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]46CONFIG_CMD_I2C=y
47CONFIG_CMD_PCI=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]48CONFIG_CMD_SPI=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]49CONFIG_CMD_USB=y
Phil Sutterd76eba62015-12-25 14:41:25 +0100[diff] [blame]50# CONFIG_CMD_SETEXPR is not set
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]51CONFIG_CMD_DHCP=y
Tom Rinie8f8d672018-04-17 09:22:31 -0400[diff] [blame]52CONFIG_CMD_TFTPPUT=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]53CONFIG_CMD_MII=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]54CONFIG_CMD_PING=y
55CONFIG_CMD_TIME=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]56CONFIG_CMD_EXT2=y
57CONFIG_CMD_FAT=y
Simon Glassc4abb4b2017-05-17 03:25:37 -0600[diff] [blame]58CONFIG_CMD_JFFS2=y
Tom Rini2b62b912018-11-13 19:54:45 -0500[diff] [blame]59CONFIG_CMD_MTDPARTS=y
Heiko Schocher09dbb852016-09-21 07:58:19 +0200[diff] [blame]60CONFIG_CMD_UBI=y
Patrick Delaunay21d3bce2017-01-27 11:00:38 +0100[diff] [blame]61CONFIG_ISO_PARTITION=y
Adam Ford710966e2020-07-03 06:48:56 -0500[diff] [blame]62CONFIG_ENV_OVERWRITE=y
Patrick Delaunayf8e932e2019-02-27 15:20:38 +0100[diff] [blame]63CONFIG_ENV_SPI_MAX_HZ=50000000
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]64CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Tom Rinia8a77502022-03-11 09:12:01 -0500[diff] [blame]65CONFIG_ARP_TIMEOUT=200
Tom Rini26011a32022-03-11 09:12:02 -0500[diff] [blame]66CONFIG_NET_RETRY_COUNT=50
Phil Sutterd76eba62015-12-25 14:41:25 +0100[diff] [blame]67CONFIG_SPL_OF_TRANSLATE=y
Stefan Roese23ccc982021-11-18 09:19:33 +0100[diff] [blame]68CONFIG_DM_I2C=y
Tom Rini8825ec42021-08-17 17:59:47 -0400[diff] [blame]69CONFIG_SYS_I2C_MVTWSI=y
Tom Rini9834b902017-03-13 13:48:42 -0400[diff] [blame]70# CONFIG_MMC is not set
Miquel Raynal2e35dbb2019-10-03 19:50:05 +0200[diff] [blame]71CONFIG_MTD=y
Phil Sutterd76eba62015-12-25 14:41:25 +0100[diff] [blame]72CONFIG_SPI_FLASH_STMICRO=y
Joe Hershberger46b7bd12018-03-30 11:52:16 -0500[diff] [blame]73CONFIG_PHY_ADDR_ENABLE=y
Mario Sixf504d1a2018-04-27 14:52:21 +0200[diff] [blame]74CONFIG_PHY_MARVELL=y
Tom Rinica22e962017-08-07 22:00:34 -0400[diff] [blame]75CONFIG_PHY_GIGE=y
Chris Packham919041c2017-08-21 20:17:03 +1200[diff] [blame]76CONFIG_MVNETA=y
Adam Ford53705472018-07-20 23:03:57 -0500[diff] [blame]77CONFIG_MII=y
Marek Behún99e296f2022-04-27 12:41:46 +0200[diff] [blame]78CONFIG_MVMDIO=y
Tom Rinif48e0252016-10-26 17:15:37 -0400[diff] [blame]79CONFIG_PCI=y
Stefan Roese3179ec62019-01-25 11:52:43 +0100[diff] [blame]80CONFIG_PCI_MVEBU=y
Pali Rohár40954732022-05-09 20:17:07 +0200[diff] [blame]81CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
Phil Sutterd76eba62015-12-25 14:41:25 +0100[diff] [blame]82CONFIG_DEBUG_UART_SHIFT=2
83CONFIG_SYS_NS16550=y
Tuomas Tynkkynen13b5cb82018-02-07 02:42:22 +0200[diff] [blame]84CONFIG_KIRKWOOD_SPI=y
Tom Rini6e9cb112016-09-08 16:31:26 -0400[diff] [blame]85CONFIG_USB=y
Phil Sutterccd45822021-03-07 22:21:23 +0100[diff] [blame]86CONFIG_USB_XHCI_HCD=y
87# CONFIG_USB_XHCI_MVEBU is not set
88CONFIG_USB_XHCI_PCI=y
Tom Rini7716cd62017-05-12 22:33:28 -0400[diff] [blame]89CONFIG_USB_EHCI_HCD=y
Tom Rini6e9cb112016-09-08 16:31:26 -0400[diff] [blame]90CONFIG_USB_STORAGE=y