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git01.mediatek.com / filogic / uboot / 4390b8ea20137a9be4cd838f5a313a057afd7cd1 / . / configs / sama5d36ek_cmp_spiflash_defconfig
blob: 04ca6a8e34f9ac80e70453e59628322b1fce3be4 [file] [log] [blame]
Wenyou Yang1646bb42017-03-24 09:26:16 +0800[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_AT91=y
Tom Rini07edfae2018-02-03 12:10:38 -0500[diff] [blame]3CONFIG_SYS_TEXT_BASE=0x26f00000
Wenyou Yang1646bb42017-03-24 09:26:16 +0800[diff] [blame]4CONFIG_TARGET_SAMA5D3XEK=y
5CONFIG_SYS_MALLOC_F_LEN=0x2000
Tom Rinie0056d72018-06-04 11:57:37 -0400[diff] [blame]6CONFIG_DEBUG_UART_BOARD_INIT=y
7CONFIG_DEBUG_UART_BASE=0xffffee00
8CONFIG_DEBUG_UART_CLOCK=132000000
Tom Rini256aa742017-06-19 09:47:40 -0400[diff] [blame]9CONFIG_DEBUG_UART=y
Adam Ford58dbf862018-02-06 07:58:59 -0600[diff] [blame]10CONFIG_ENV_VARS_UBOOT_CONFIG=y
Tom Rinif2260382018-08-16 08:16:24 -0400[diff] [blame]11CONFIG_NR_DRAM_BANKS=1
Wenyou Yang1646bb42017-03-24 09:26:16 +0800[diff] [blame]12CONFIG_FIT=y
Wenyou Yange035ea72017-09-14 11:07:44 +0800[diff] [blame]13CONFIG_SPI_BOOT=y
Wenyou Yang1646bb42017-03-24 09:26:16 +0800[diff] [blame]14CONFIG_BOOTDELAY=3
Sam Protsenkobd7bffe2017-08-14 20:22:17 +0300[diff] [blame]15CONFIG_USE_BOOTARGS=y
Eugen Hristev68b37ab2018-04-24 12:00:16 +0300[diff] [blame]16CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256K(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
Wenyou Yang1646bb42017-03-24 09:26:16 +0800[diff] [blame]17# CONFIG_CONSOLE_MUX is not set
18CONFIG_SYS_CONSOLE_IS_IN_ENV=y
19# CONFIG_DISPLAY_BOARDINFO is not set
20CONFIG_HUSH_PARSER=y
21CONFIG_CMD_BOOTZ=y
22# CONFIG_CMD_IMI is not set
Wenyou Yang1646bb42017-03-24 09:26:16 +0800[diff] [blame]23# CONFIG_CMD_LOADS is not set
24CONFIG_CMD_MMC=y
Tom Rini00448d22017-07-28 21:31:42 -0400[diff] [blame]25CONFIG_CMD_NAND=y
26CONFIG_CMD_NAND_TRIMFFS=y
Wenyou Yang1646bb42017-03-24 09:26:16 +0800[diff] [blame]27CONFIG_CMD_SF=y
Wenyou Yang1646bb42017-03-24 09:26:16 +0800[diff] [blame]28CONFIG_CMD_DHCP=y
29CONFIG_CMD_MII=y
30CONFIG_CMD_PING=y
31CONFIG_CMD_FAT=y
32CONFIG_OF_CONTROL=y
Tom Rini74060322018-09-03 15:26:12 -0400[diff] [blame]33CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp"
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]34CONFIG_ENV_IS_IN_SPI_FLASH=y
Alex Kiernana410d6e2018-04-01 16:37:53 +0000[diff] [blame]35CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
Wenyou Yang1646bb42017-03-24 09:26:16 +0800[diff] [blame]36CONFIG_DM=y
37CONFIG_CLK=y
38CONFIG_CLK_AT91=y
Wenyou Yang1646bb42017-03-24 09:26:16 +0800[diff] [blame]39CONFIG_AT91_H32MX=y
40CONFIG_DM_GPIO=y
41CONFIG_AT91_GPIO=y
42CONFIG_DM_MMC=y
43CONFIG_GENERIC_ATMEL_MCI=y
Adam Ford9c519182018-07-08 08:11:07 -0500[diff] [blame]44CONFIG_NAND=y
45CONFIG_NAND_ATMEL=y
Wenyou Yang1646bb42017-03-24 09:26:16 +0800[diff] [blame]46CONFIG_DM_SPI_FLASH=y
47CONFIG_SPI_FLASH=y
48CONFIG_SPI_FLASH_ATMEL=y
49CONFIG_DM_ETH=y
50CONFIG_MACB=y
51CONFIG_PINCTRL=y
52CONFIG_PINCTRL_AT91=y
53CONFIG_DM_SERIAL=y
Wenyou Yang1646bb42017-03-24 09:26:16 +0800[diff] [blame]54CONFIG_DEBUG_UART_ATMEL=y
Wenyou Yang1646bb42017-03-24 09:26:16 +0800[diff] [blame]55CONFIG_DEBUG_UART_ANNOUNCE=y
56CONFIG_ATMEL_USART=y
Adam Ford4e96ff82018-04-15 13:51:26 -0400[diff] [blame]57CONFIG_SPI=y
Wenyou Yang1646bb42017-03-24 09:26:16 +0800[diff] [blame]58CONFIG_DM_SPI=y
Wenyou.Yang@microchip.com272167d2017-08-15 17:40:27 +0800[diff] [blame]59CONFIG_TIMER=y
60CONFIG_ATMEL_PIT_TIMER=y
Wenyou Yang3c3be532017-09-18 15:25:58 +0800[diff] [blame]61CONFIG_DM_VIDEO=y
62CONFIG_ATMEL_HLCD=y
Tom Rinid8532af2017-06-02 11:03:50 -0400[diff] [blame]63CONFIG_FAT_WRITE=y