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git01.mediatek.com / filogic / uboot / 435c190d43dc2b8e2d98bf1fed10ba77fa8546d5 / . / arch / arm / dts / am437x-idk-evm-u-boot.dtsi
blob: 7c9f80e7ba2f2eb4d704164c238e3758913800d6 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Vignesh Ra611ffc2018-03-26 13:27:02 +0530[diff] [blame]2/*
Nishanth Menoneaa39c62023-11-01 15:56:03 -0500[diff] [blame]3 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
Vignesh Ra611ffc2018-03-26 13:27:02 +0530[diff] [blame]4 */
5
Jean-Jacques Hiblot00c7a962018-12-04 11:30:52 +0100[diff] [blame]6#include "am4372-u-boot.dtsi"
7
Vignesh Ra611ffc2018-03-26 13:27:02 +0530[diff] [blame]8/{
9 ocp {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]10 bootph-pre-ram;
Vignesh Ra611ffc2018-03-26 13:27:02 +0530[diff] [blame]11 };
Tero Kristo30bc6d82019-09-27 19:14:28 +0300[diff] [blame]12
13 xtal25mhz: xtal25mhz {
14 compatible = "fixed-clock";
15 #clock-cells = <0>;
16 clock-frequency = <25000000>;
17 };
Vignesh Ra611ffc2018-03-26 13:27:02 +0530[diff] [blame]18};
19
20&uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]21 bootph-pre-ram;
Vignesh Ra611ffc2018-03-26 13:27:02 +0530[diff] [blame]22};
23
24&i2c0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]25 bootph-pre-ram;
Tero Kristo30bc6d82019-09-27 19:14:28 +0300[diff] [blame]26
27 cdce913: cdce913@65 {
28 compatible = "ti,cdce913";
29 reg = <0x65>;
30 clocks = <&xtal25mhz>;
31 #clock-cells = <1>;
32 xtal-load-pf = <0>;
33 };
Vignesh Ra611ffc2018-03-26 13:27:02 +0530[diff] [blame]34};
35
36&mmc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]37 bootph-pre-ram;
Vignesh Ra611ffc2018-03-26 13:27:02 +0530[diff] [blame]38};