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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Tom Warren7a3fa012013-01-28 13:32:13 +00002/*
3 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
Tom Warren7a3fa012013-01-28 13:32:13 +00004 */
5
6#ifndef _TEGRA114_COMMON_H_
7#define _TEGRA114_COMMON_H_
8#include "tegra-common.h"
9
10/*
11 * NS16550 Configuration
12 */
13#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
14
Tom Warren7a3fa012013-01-28 13:32:13 +000015/*
16 * Miscellaneous configurable options
17 */
Tom Rini1d20f4e2022-12-04 10:13:55 -050018#define CFG_STACKBASE 0x83800000 /* 56MB */
Tom Warren7a3fa012013-01-28 13:32:13 +000019
20/*-----------------------------------------------------------------------
21 * Physical Memory Map
22 */
Tom Warren7a3fa012013-01-28 13:32:13 +000023
24/*
25 * Memory layout for where various images get loaded by boot scripts:
26 *
27 * scriptaddr can be pretty much anywhere that doesn't conflict with something
28 * else. Put it above BOOTMAPSZ to eliminate conflicts.
29 *
Stephen Warren7434dfe2014-02-05 09:24:59 -070030 * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
31 * something else. Put it above BOOTMAPSZ to eliminate conflicts.
32 *
Tom Warren7a3fa012013-01-28 13:32:13 +000033 * kernel_addr_r must be within the first 128M of RAM in order for the
34 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
35 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
36 * should not overlap that area, or the kernel will have to copy itself
37 * somewhere else before decompression. Similarly, the address of any other
38 * data passed to the kernel shouldn't overlap the start of RAM. Pushing
Jonathan Hunter80239362019-02-12 16:03:14 +000039 * this up to 32M allows for a sizable kernel to be decompressed below the
Tom Warren7a3fa012013-01-28 13:32:13 +000040 * compressed load address.
41 *
Jonathan Hunter80239362019-02-12 16:03:14 +000042 * fdt_addr_r simply shouldn't overlap anything else. Choosing 48M allows for
43 * the compressed kernel to be up to 32M too.
Tom Warren7a3fa012013-01-28 13:32:13 +000044 *
Jonathan Hunter80239362019-02-12 16:03:14 +000045 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows
Tom Warren7a3fa012013-01-28 13:32:13 +000046 * for the FDT/DTB to be up to 1M, which is hopefully plenty.
47 */
48#define MEM_LAYOUT_ENV_SETTINGS \
49 "scriptaddr=0x90000000\0" \
Stephen Warren7434dfe2014-02-05 09:24:59 -070050 "pxefile_addr_r=0x90100000\0" \
Tom Rini9004ee02021-08-23 10:25:30 -040051 "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
Peter Robinson637ac012020-04-02 00:28:54 +010052 "fdtfile=" FDTFILE "\0" \
Jonathan Hunter80239362019-02-12 16:03:14 +000053 "fdt_addr_r=0x83000000\0" \
54 "ramdisk_addr_r=0x83100000\0"
Tom Warren7a3fa012013-01-28 13:32:13 +000055
56/* Defines for SPL */
Tom Warren7a3fa012013-01-28 13:32:13 +000057
Tom Warren7a3fa012013-01-28 13:32:13 +000058#endif /* _TEGRA114_COMMON_H_ */