blob: 53c231a5e46d048e5a5fe33912cd2737686d220d [file] [log] [blame]
wdenkf8062712005-01-09 23:16:25 +00001/*
2 * (C) Copyright 2004
3 * Texas Instruments, <www.ti.com>
4 * Richard Woodruff <r-woodruff2@ti.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#ifndef _OMAP24XX_SYS_INFO_H_
26#define _OMAP24XX_SYS_INFO_H_
27
28typedef struct h4_system_data {
29 /* base board info */
30 u32 base_b_rev; /* rev from base board i2c */
31 /* cpu board info */
32 u32 cpu_b_rev; /* rev from cpu board i2c */
33 u32 cpu_b_mux; /* mux type on daughter board */
34 u32 cpu_b_ddr_type; /* mem type */
35 u32 cpu_b_ddr_speed; /* ddr speed rating */
36 u32 cpu_b_switches; /* boot ctrl switch settings */
37 /* cpu info */
38 u32 cpu_type; /* type of cpu; 2420, 2422, 2430,...*/
39 u32 cpu_rev; /* rev of given cpu; ES1, ES2,...*/
40} h4_sys_data;
41
Wolfgang Denke1e46792005-09-25 18:41:04 +020042#define XDR_POP 5 /* package on package part */
43#define SDR_DISCRETE 4 /* 128M memory SDR module*/
wdenkf8062712005-01-09 23:16:25 +000044#define DDR_STACKED 3 /* stacked part on 2422 */
45#define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */
46#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */
47
48#define DDR_100 100 /* type found on most mem d-boards */
49#define DDR_111 111 /* some combo parts */
50#define DDR_133 133 /* most combo, some mem d-boards */
51#define DDR_165 165 /* future parts */
52
53#define CPU_2420 0x2420
Wolfgang Denke1e46792005-09-25 18:41:04 +020054#define CPU_2422 0x2422 /* 2420 + 64M stacked */
55#define CPU_2423 0x2423 /* 2420 + 96M stacked */
wdenkf8062712005-01-09 23:16:25 +000056
57#define CPU_2422_ES1 1
58#define CPU_2422_ES2 2
59#define CPU_2420_ES1 1
60#define CPU_2420_ES2 2
Wolfgang Denke1e46792005-09-25 18:41:04 +020061#define CPU_2420_2422_ES1 1
wdenkf8062712005-01-09 23:16:25 +000062
63#define CPU_2420_CHIPID 0x0B5D9000
64#define CPU_24XX_ID_MASK 0x0FFFF000
65#define CPU_242X_REV_MASK 0xF0000000
Wolfgang Denke1e46792005-09-25 18:41:04 +020066#define CPU_242X_PID_MASK 0x000F0000
wdenkf8062712005-01-09 23:16:25 +000067
68#define BOARD_H4_MENELAUS 1
69#define BOARD_H4_SDP 2
70
71#define GPMC_MUXED 1
72#define GPMC_NONMUXED 0
73
74#define TYPE_NAND 0x800 /* bit pos for nand in gpmc reg */
75#define TYPE_NOR 0x000
76
77#define WIDTH_8BIT 0x0000
78#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */
79
80#define I2C_MENELAUS 0x72 /* i2c id for companion chip */
81
82#endif