blob: 1aa267e76a5343e54c1c615975674bb60c97d651 [file] [log] [blame]
Patrick Delaunay8c6e6132019-11-06 16:16:33 +01001/* SPDX-License-Identifier: GPL-2.0 */
Patrice Chotarde5f82cf2017-07-18 09:29:02 +02002/*
3 * This header provides constants for the STM32F7 RCC IP
4 */
5
6#ifndef _DT_BINDINGS_MFD_STM32F7_RCC_H
7#define _DT_BINDINGS_MFD_STM32F7_RCC_H
8
9/* AHB1 */
10#define STM32F7_RCC_AHB1_GPIOA 0
11#define STM32F7_RCC_AHB1_GPIOB 1
12#define STM32F7_RCC_AHB1_GPIOC 2
13#define STM32F7_RCC_AHB1_GPIOD 3
14#define STM32F7_RCC_AHB1_GPIOE 4
15#define STM32F7_RCC_AHB1_GPIOF 5
16#define STM32F7_RCC_AHB1_GPIOG 6
17#define STM32F7_RCC_AHB1_GPIOH 7
18#define STM32F7_RCC_AHB1_GPIOI 8
19#define STM32F7_RCC_AHB1_GPIOJ 9
20#define STM32F7_RCC_AHB1_GPIOK 10
21#define STM32F7_RCC_AHB1_CRC 12
22#define STM32F7_RCC_AHB1_BKPSRAM 18
23#define STM32F7_RCC_AHB1_DTCMRAM 20
24#define STM32F7_RCC_AHB1_DMA1 21
25#define STM32F7_RCC_AHB1_DMA2 22
26#define STM32F7_RCC_AHB1_DMA2D 23
27#define STM32F7_RCC_AHB1_ETHMAC 25
28#define STM32F7_RCC_AHB1_ETHMACTX 26
29#define STM32F7_RCC_AHB1_ETHMACRX 27
30#define STM32FF_RCC_AHB1_ETHMACPTP 28
31#define STM32F7_RCC_AHB1_OTGHS 29
32#define STM32F7_RCC_AHB1_OTGHSULPI 30
33
34#define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8))
35#define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit)
36
Patrice Chotarde5f82cf2017-07-18 09:29:02 +020037/* AHB2 */
38#define STM32F7_RCC_AHB2_DCMI 0
39#define STM32F7_RCC_AHB2_CRYP 4
40#define STM32F7_RCC_AHB2_HASH 5
41#define STM32F7_RCC_AHB2_RNG 6
42#define STM32F7_RCC_AHB2_OTGFS 7
43
44#define STM32F7_AHB2_RESET(bit) (STM32F7_RCC_AHB2_##bit + (0x14 * 8))
45#define STM32F7_AHB2_CLOCK(bit) (STM32F7_RCC_AHB2_##bit + 0x20)
46
47/* AHB3 */
48#define STM32F7_RCC_AHB3_FMC 0
49#define STM32F7_RCC_AHB3_QSPI 1
50
51#define STM32F7_AHB3_RESET(bit) (STM32F7_RCC_AHB3_##bit + (0x18 * 8))
52#define STM32F7_AHB3_CLOCK(bit) (STM32F7_RCC_AHB3_##bit + 0x40)
53
54/* APB1 */
55#define STM32F7_RCC_APB1_TIM2 0
56#define STM32F7_RCC_APB1_TIM3 1
57#define STM32F7_RCC_APB1_TIM4 2
58#define STM32F7_RCC_APB1_TIM5 3
59#define STM32F7_RCC_APB1_TIM6 4
60#define STM32F7_RCC_APB1_TIM7 5
61#define STM32F7_RCC_APB1_TIM12 6
62#define STM32F7_RCC_APB1_TIM13 7
63#define STM32F7_RCC_APB1_TIM14 8
64#define STM32F7_RCC_APB1_LPTIM1 9
65#define STM32F7_RCC_APB1_WWDG 11
Dario Binacchi9bed2182023-09-03 22:48:40 +020066#define STM32F7_RCC_APB1_CAN3 13
Patrice Chotarde5f82cf2017-07-18 09:29:02 +020067#define STM32F7_RCC_APB1_SPI2 14
68#define STM32F7_RCC_APB1_SPI3 15
69#define STM32F7_RCC_APB1_SPDIFRX 16
70#define STM32F7_RCC_APB1_UART2 17
71#define STM32F7_RCC_APB1_UART3 18
72#define STM32F7_RCC_APB1_UART4 19
73#define STM32F7_RCC_APB1_UART5 20
74#define STM32F7_RCC_APB1_I2C1 21
75#define STM32F7_RCC_APB1_I2C2 22
76#define STM32F7_RCC_APB1_I2C3 23
77#define STM32F7_RCC_APB1_I2C4 24
78#define STM32F7_RCC_APB1_CAN1 25
79#define STM32F7_RCC_APB1_CAN2 26
80#define STM32F7_RCC_APB1_CEC 27
81#define STM32F7_RCC_APB1_PWR 28
82#define STM32F7_RCC_APB1_DAC 29
83#define STM32F7_RCC_APB1_UART7 30
84#define STM32F7_RCC_APB1_UART8 31
85
86#define STM32F7_APB1_RESET(bit) (STM32F7_RCC_APB1_##bit + (0x20 * 8))
87#define STM32F7_APB1_CLOCK(bit) (STM32F7_RCC_APB1_##bit + 0x80)
88
89/* APB2 */
90#define STM32F7_RCC_APB2_TIM1 0
91#define STM32F7_RCC_APB2_TIM8 1
92#define STM32F7_RCC_APB2_USART1 4
93#define STM32F7_RCC_APB2_USART6 5
Patrice Chotard369d4832017-11-15 13:14:52 +010094#define STM32F7_RCC_APB2_SDMMC2 7
Patrice Chotarde5f82cf2017-07-18 09:29:02 +020095#define STM32F7_RCC_APB2_ADC1 8
96#define STM32F7_RCC_APB2_ADC2 9
97#define STM32F7_RCC_APB2_ADC3 10
98#define STM32F7_RCC_APB2_SDMMC1 11
99#define STM32F7_RCC_APB2_SPI1 12
100#define STM32F7_RCC_APB2_SPI4 13
101#define STM32F7_RCC_APB2_SYSCFG 14
102#define STM32F7_RCC_APB2_TIM9 16
103#define STM32F7_RCC_APB2_TIM10 17
104#define STM32F7_RCC_APB2_TIM11 18
105#define STM32F7_RCC_APB2_SPI5 20
106#define STM32F7_RCC_APB2_SPI6 21
107#define STM32F7_RCC_APB2_SAI1 22
108#define STM32F7_RCC_APB2_SAI2 23
109#define STM32F7_RCC_APB2_LTDC 26
Patrice Chotarde199c3a2018-02-08 17:20:51 +0100110#define STM32F7_RCC_APB2_DSI 27
Patrice Chotarde5f82cf2017-07-18 09:29:02 +0200111
112#define STM32F7_APB2_RESET(bit) (STM32F7_RCC_APB2_##bit + (0x24 * 8))
113#define STM32F7_APB2_CLOCK(bit) (STM32F7_RCC_APB2_##bit + 0xA0)
114
115#endif /* _DT_BINDINGS_MFD_STM32F7_RCC_H */