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git01.mediatek.com / filogic / uboot / 42c5ecc37c410094caf50628c75b5568119311fa / . / drivers / reset / reset-ipq4019.c
blob: 15858f3cb1ee5117db312e17ff71168ea9dea883 [file] [log] [blame]
Robert Markof5edc7a2020-09-10 16:00:02 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2020 Sartura Ltd.
4 *
5 * Author: Robert Marko <robert.marko@sartura.hr>
6 *
7 * Based on Linux driver
8 */
9
10#include <asm/io.h>
11#include <common.h>
12#include <dm.h>
13#include <dt-bindings/reset/qcom,ipq4019-reset.h>
14#include <reset-uclass.h>
15#include <linux/bitops.h>
16#include <malloc.h>
17
18struct ipq4019_reset_priv {
19 phys_addr_t base;
20};
21
22struct qcom_reset_map {
23 unsigned int reg;
24 u8 bit;
25};
26
27static const struct qcom_reset_map gcc_ipq4019_resets[] = {
28 [WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 },
29 [WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 },
30 [WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 },
31 [WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 },
32 [WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 },
33 [WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 },
34 [WIFI1_CPU_INIT_RESET] = { 0x20008, 5 },
35 [WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 },
36 [WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 },
37 [WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 },
38 [WIFI1_CORE_WARM_RESET] = { 0x20008, 1 },
39 [WIFI1_CORE_COLD_RESET] = { 0x20008, 0 },
40 [USB3_UNIPHY_PHY_ARES] = { 0x1e038, 5 },
41 [USB3_HSPHY_POR_ARES] = { 0x1e038, 4 },
42 [USB3_HSPHY_S_ARES] = { 0x1e038, 2 },
43 [USB2_HSPHY_POR_ARES] = { 0x1e01c, 4 },
44 [USB2_HSPHY_S_ARES] = { 0x1e01c, 2 },
45 [PCIE_PHY_AHB_ARES] = { 0x1d010, 11 },
46 [PCIE_AHB_ARES] = { 0x1d010, 10 },
47 [PCIE_PWR_ARES] = { 0x1d010, 9 },
48 [PCIE_PIPE_STICKY_ARES] = { 0x1d010, 8 },
49 [PCIE_AXI_M_STICKY_ARES] = { 0x1d010, 7 },
50 [PCIE_PHY_ARES] = { 0x1d010, 6 },
51 [PCIE_PARF_XPU_ARES] = { 0x1d010, 5 },
52 [PCIE_AXI_S_XPU_ARES] = { 0x1d010, 4 },
53 [PCIE_AXI_M_VMIDMT_ARES] = { 0x1d010, 3 },
54 [PCIE_PIPE_ARES] = { 0x1d010, 2 },
55 [PCIE_AXI_S_ARES] = { 0x1d010, 1 },
56 [PCIE_AXI_M_ARES] = { 0x1d010, 0 },
57 [ESS_RESET] = { 0x12008, 0},
58 [GCC_BLSP1_BCR] = {0x01000, 0},
59 [GCC_BLSP1_QUP1_BCR] = {0x02000, 0},
60 [GCC_BLSP1_UART1_BCR] = {0x02038, 0},
61 [GCC_BLSP1_QUP2_BCR] = {0x03008, 0},
62 [GCC_BLSP1_UART2_BCR] = {0x03028, 0},
63 [GCC_BIMC_BCR] = {0x04000, 0},
64 [GCC_TLMM_BCR] = {0x05000, 0},
65 [GCC_IMEM_BCR] = {0x0E000, 0},
66 [GCC_ESS_BCR] = {0x12008, 0},
67 [GCC_PRNG_BCR] = {0x13000, 0},
68 [GCC_BOOT_ROM_BCR] = {0x13008, 0},
69 [GCC_CRYPTO_BCR] = {0x16000, 0},
70 [GCC_SDCC1_BCR] = {0x18000, 0},
71 [GCC_SEC_CTRL_BCR] = {0x1A000, 0},
72 [GCC_AUDIO_BCR] = {0x1B008, 0},
73 [GCC_QPIC_BCR] = {0x1C000, 0},
74 [GCC_PCIE_BCR] = {0x1D000, 0},
75 [GCC_USB2_BCR] = {0x1E008, 0},
76 [GCC_USB2_PHY_BCR] = {0x1E018, 0},
77 [GCC_USB3_BCR] = {0x1E024, 0},
78 [GCC_USB3_PHY_BCR] = {0x1E034, 0},
79 [GCC_SYSTEM_NOC_BCR] = {0x21000, 0},
80 [GCC_PCNOC_BCR] = {0x2102C, 0},
81 [GCC_DCD_BCR] = {0x21038, 0},
82 [GCC_SNOC_BUS_TIMEOUT0_BCR] = {0x21064, 0},
83 [GCC_SNOC_BUS_TIMEOUT1_BCR] = {0x2106C, 0},
84 [GCC_SNOC_BUS_TIMEOUT2_BCR] = {0x21074, 0},
85 [GCC_SNOC_BUS_TIMEOUT3_BCR] = {0x2107C, 0},
86 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = {0x21084, 0},
87 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = {0x2108C, 0},
88 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = {0x21094, 0},
89 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = {0x2109C, 0},
90 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = {0x210A4, 0},
91 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = {0x210AC, 0},
92 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = {0x210B4, 0},
93 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = {0x210BC, 0},
94 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = {0x210C4, 0},
95 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = {0x210CC, 0},
96 [GCC_TCSR_BCR] = {0x22000, 0},
97 [GCC_MPM_BCR] = {0x24000, 0},
98 [GCC_SPDM_BCR] = {0x25000, 0},
99};
100
101static int ipq4019_reset_assert(struct reset_ctl *rst)
102{
103 struct ipq4019_reset_priv *priv = dev_get_priv(rst->dev);
104 const struct qcom_reset_map *reset_map = gcc_ipq4019_resets;
105 const struct qcom_reset_map *map;
106 u32 value;
107
108 map = &reset_map[rst->id];
109
110 value = readl(priv->base + map->reg);
111 value |= BIT(map->bit);
112 writel(value, priv->base + map->reg);
113
114 return 0;
115}
116
117static int ipq4019_reset_deassert(struct reset_ctl *rst)
118{
119 struct ipq4019_reset_priv *priv = dev_get_priv(rst->dev);
120 const struct qcom_reset_map *reset_map = gcc_ipq4019_resets;
121 const struct qcom_reset_map *map;
122 u32 value;
123
124 map = &reset_map[rst->id];
125
126 value = readl(priv->base + map->reg);
127 value &= ~BIT(map->bit);
128 writel(value, priv->base + map->reg);
129
130 return 0;
131}
132
133static int ipq4019_reset_free(struct reset_ctl *rst)
134{
135 return 0;
136}
137
138static int ipq4019_reset_request(struct reset_ctl *rst)
139{
140 return 0;
141}
142
143static const struct reset_ops ipq4019_reset_ops = {
144 .request = ipq4019_reset_request,
145 .rfree = ipq4019_reset_free,
146 .rst_assert = ipq4019_reset_assert,
147 .rst_deassert = ipq4019_reset_deassert,
148};
149
150static const struct udevice_id ipq4019_reset_ids[] = {
151 { .compatible = "qcom,gcc-reset-ipq4019" },
152 { }
153};
154
155static int ipq4019_reset_probe(struct udevice *dev)
156{
157 struct ipq4019_reset_priv *priv = dev_get_priv(dev);
158
159 priv->base = dev_read_addr(dev);
160 if (priv->base == FDT_ADDR_T_NONE)
161 return -EINVAL;
162
163 return 0;
164}
165
166U_BOOT_DRIVER(ipq4019_reset) = {
167 .name = "ipq4019_reset",
168 .id = UCLASS_RESET,
169 .of_match = ipq4019_reset_ids,
170 .ops = &ipq4019_reset_ops,
171 .probe = ipq4019_reset_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700[diff] [blame]172 .priv_auto = sizeof(struct ipq4019_reset_priv),
Robert Markof5edc7a2020-09-10 16:00:02 +0200[diff] [blame]173};