Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (C) 2012 Atmel Corporation |
| 3 | * |
| 4 | * See file CREDITS for list of people who contributed to this |
| 5 | * project. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | */ |
| 22 | |
| 23 | #include <common.h> |
| 24 | #include <asm/arch/at91_common.h> |
| 25 | #include <asm/arch/at91_pmc.h> |
| 26 | #include <asm/arch/gpio.h> |
| 27 | #include <asm/io.h> |
| 28 | |
| 29 | unsigned int get_chip_id(void) |
| 30 | { |
| 31 | /* The 0x40 is the offset of cidr in DBGU */ |
| 32 | return readl(ATMEL_BASE_DBGU + 0x40) & ~ARCH_ID_VERSION_MASK; |
| 33 | } |
| 34 | |
| 35 | unsigned int get_extension_chip_id(void) |
| 36 | { |
| 37 | /* The 0x44 is the offset of exid in DBGU */ |
| 38 | return readl(ATMEL_BASE_DBGU + 0x44); |
| 39 | } |
| 40 | |
| 41 | unsigned int has_emac1() |
| 42 | { |
| 43 | return cpu_is_at91sam9x25(); |
| 44 | } |
| 45 | |
| 46 | unsigned int has_emac0() |
| 47 | { |
| 48 | return !(cpu_is_at91sam9g15()); |
| 49 | } |
| 50 | |
| 51 | unsigned int has_lcdc() |
| 52 | { |
| 53 | return cpu_is_at91sam9g15() || cpu_is_at91sam9g35() |
| 54 | || cpu_is_at91sam9x35(); |
| 55 | } |
| 56 | |
| 57 | char *get_cpu_name() |
| 58 | { |
| 59 | unsigned int extension_id = get_extension_chip_id(); |
| 60 | |
| 61 | if (cpu_is_at91sam9x5()) { |
| 62 | switch (extension_id) { |
| 63 | case ARCH_EXID_AT91SAM9G15: |
| 64 | return CONFIG_SYS_AT91_G15_CPU_NAME; |
| 65 | case ARCH_EXID_AT91SAM9G25: |
| 66 | return CONFIG_SYS_AT91_G25_CPU_NAME; |
| 67 | case ARCH_EXID_AT91SAM9G35: |
| 68 | return CONFIG_SYS_AT91_G35_CPU_NAME; |
| 69 | case ARCH_EXID_AT91SAM9X25: |
| 70 | return CONFIG_SYS_AT91_X25_CPU_NAME; |
| 71 | case ARCH_EXID_AT91SAM9X35: |
| 72 | return CONFIG_SYS_AT91_X35_CPU_NAME; |
| 73 | default: |
| 74 | return CONFIG_SYS_AT91_UNKNOWN_CPU; |
| 75 | } |
| 76 | } else { |
| 77 | return CONFIG_SYS_AT91_UNKNOWN_CPU; |
| 78 | } |
| 79 | } |
| 80 | |
| 81 | void at91_seriald_hw_init(void) |
| 82 | { |
| 83 | at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; |
| 84 | |
| 85 | at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */ |
| 86 | at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */ |
| 87 | |
| 88 | writel(1 << ATMEL_ID_SYS, &pmc->pcer); |
| 89 | } |
| 90 | |
| 91 | void at91_serial0_hw_init(void) |
| 92 | { |
| 93 | at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; |
| 94 | |
| 95 | at91_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD */ |
| 96 | at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD */ |
| 97 | |
| 98 | writel(1 << ATMEL_ID_USART0, &pmc->pcer); |
| 99 | } |
| 100 | |
| 101 | void at91_serial1_hw_init(void) |
| 102 | { |
| 103 | at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; |
| 104 | |
| 105 | at91_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD */ |
| 106 | at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD */ |
| 107 | |
| 108 | writel(1 << ATMEL_ID_USART1, &pmc->pcer); |
| 109 | } |
| 110 | |
| 111 | void at91_serial2_hw_init(void) |
| 112 | { |
| 113 | at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; |
| 114 | |
| 115 | at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD */ |
| 116 | at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD */ |
| 117 | |
| 118 | writel(1 << ATMEL_ID_USART2, &pmc->pcer); |
| 119 | } |
| 120 | |
| 121 | #ifdef CONFIG_ATMEL_SPI |
| 122 | void at91_spi0_hw_init(unsigned long cs_mask) |
| 123 | { |
| 124 | at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_PMC_BASE; |
| 125 | |
| 126 | at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */ |
| 127 | at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */ |
| 128 | at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */ |
| 129 | |
| 130 | /* Enable clock */ |
| 131 | writel(1 << ATMEL_ID_SPI0, &pmc->pcer); |
| 132 | |
| 133 | if (cs_mask & (1 << 0)) |
| 134 | at91_set_a_periph(AT91_PIO_PORTA, 14, 0); |
| 135 | if (cs_mask & (1 << 1)) |
| 136 | at91_set_b_periph(AT91_PIO_PORTA, 7, 0); |
| 137 | if (cs_mask & (1 << 2)) |
| 138 | at91_set_b_periph(AT91_PIO_PORTA, 1, 0); |
| 139 | if (cs_mask & (1 << 3)) |
| 140 | at91_set_b_periph(AT91_PIO_PORTB, 3, 0); |
| 141 | if (cs_mask & (1 << 4)) |
| 142 | at91_set_pio_output(AT91_PIO_PORTA, 14, 0); |
| 143 | if (cs_mask & (1 << 5)) |
| 144 | at91_set_pio_output(AT91_PIO_PORTA, 7, 0); |
| 145 | if (cs_mask & (1 << 6)) |
| 146 | at91_set_pio_output(AT91_PIO_PORTA, 1, 0); |
| 147 | if (cs_mask & (1 << 7)) |
| 148 | at91_set_pio_output(AT91_PIO_PORTB, 3, 0); |
| 149 | } |
| 150 | |
| 151 | void at91_spi1_hw_init(unsigned long cs_mask) |
| 152 | { |
| 153 | at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_PMC_BASE; |
| 154 | |
| 155 | at91_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */ |
| 156 | at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */ |
| 157 | at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */ |
| 158 | |
| 159 | /* Enable clock */ |
| 160 | writel(1 << ATMEL_ID_SPI1, &pmc->pcer); |
| 161 | |
| 162 | if (cs_mask & (1 << 0)) |
| 163 | at91_set_b_periph(AT91_PIO_PORTA, 8, 0); |
| 164 | if (cs_mask & (1 << 1)) |
| 165 | at91_set_b_periph(AT91_PIO_PORTA, 0, 0); |
| 166 | if (cs_mask & (1 << 2)) |
| 167 | at91_set_b_periph(AT91_PIO_PORTA, 31, 0); |
| 168 | if (cs_mask & (1 << 3)) |
| 169 | at91_set_b_periph(AT91_PIO_PORTA, 30, 0); |
| 170 | if (cs_mask & (1 << 4)) |
| 171 | at91_set_pio_output(AT91_PIO_PORTA, 8, 0); |
| 172 | if (cs_mask & (1 << 5)) |
| 173 | at91_set_pio_output(AT91_PIO_PORTA, 0, 0); |
| 174 | if (cs_mask & (1 << 6)) |
| 175 | at91_set_pio_output(AT91_PIO_PORTA, 31, 0); |
| 176 | if (cs_mask & (1 << 7)) |
| 177 | at91_set_pio_output(AT91_PIO_PORTA, 30, 0); |
| 178 | } |
| 179 | #endif |
| 180 | |
| 181 | #ifdef CONFIG_MACB |
| 182 | void at91_macb_hw_init(void) |
| 183 | { |
| 184 | at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; |
| 185 | |
| 186 | if (has_emac0()) { |
| 187 | /* Enable EMAC0 clock */ |
| 188 | writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); |
| 189 | /* EMAC0 pins setup */ |
| 190 | at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* ETXCK */ |
| 191 | at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* ERXDV */ |
| 192 | at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ERX0 */ |
| 193 | at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* ERX1 */ |
| 194 | at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ERXER */ |
| 195 | at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ETXEN */ |
| 196 | at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ETX0 */ |
| 197 | at91_set_a_periph(AT91_PIO_PORTB, 10, 0); /* ETX1 */ |
| 198 | at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* EMDIO */ |
| 199 | at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* EMDC */ |
| 200 | } |
| 201 | |
| 202 | if (has_emac1()) { |
| 203 | /* Enable EMAC1 clock */ |
| 204 | writel(1 << ATMEL_ID_EMAC1, &pmc->pcer); |
| 205 | /* EMAC1 pins setup */ |
| 206 | at91_set_b_periph(AT91_PIO_PORTC, 29, 0); /* ETXCK */ |
| 207 | at91_set_b_periph(AT91_PIO_PORTC, 28, 0); /* ECRSDV */ |
| 208 | at91_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ERXO */ |
| 209 | at91_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ERX1 */ |
| 210 | at91_set_b_periph(AT91_PIO_PORTC, 16, 0); /* ERXER */ |
| 211 | at91_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ETXEN */ |
| 212 | at91_set_b_periph(AT91_PIO_PORTC, 18, 0); /* ETX0 */ |
| 213 | at91_set_b_periph(AT91_PIO_PORTC, 19, 0); /* ETX1 */ |
| 214 | at91_set_b_periph(AT91_PIO_PORTC, 31, 0); /* EMDIO */ |
| 215 | at91_set_b_periph(AT91_PIO_PORTC, 30, 0); /* EMDC */ |
| 216 | } |
| 217 | |
| 218 | #ifndef CONFIG_RMII |
| 219 | /* Only emac0 support MII */ |
| 220 | if (has_emac0()) { |
| 221 | at91_set_b_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */ |
| 222 | at91_set_b_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */ |
| 223 | at91_set_b_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */ |
| 224 | at91_set_b_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */ |
| 225 | at91_set_b_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */ |
| 226 | at91_set_b_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */ |
| 227 | at91_set_b_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */ |
| 228 | at91_set_b_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */ |
| 229 | } |
| 230 | #endif |
| 231 | } |
| 232 | #endif |