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git01.mediatek.com / filogic / uboot / 42a89ecc3e9401d9d219e197ef7d64373a8ba72b / . / drivers / pinctrl / tegra / pinmux-tegra20.c
blob: c1f86476b9ef168d096244cfdc9c785d0998f050 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Simon Glassfa516f62011-08-30 06:23:14 +0000[diff] [blame]2/*
3 * Copyright (c) 2011 The Chromium OS Authors.
Simon Glassfa516f62011-08-30 06:23:14 +0000[diff] [blame]4 */
5
Allen Martin55d98a12012-08-31 08:30:00 +0000[diff] [blame]6/* Tegra20 pin multiplexing functions */
Simon Glassfa516f62011-08-30 06:23:14 +0000[diff] [blame]7
8#include <asm/io.h>
Simon Glassfa516f62011-08-30 06:23:14 +0000[diff] [blame]9#include <asm/arch/pinmux.h>
Simon Glassfa516f62011-08-30 06:23:14 +0000[diff] [blame]10
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]11/*
12 * This defines the order of the pin mux control bits in the registers. For
13 * some reason there is no correspendence between the tristate, pin mux and
14 * pullup/pulldown registers.
15 */
16enum pmux_ctlid {
17 /* 0: APB_MISC_PP_PIN_MUX_CTL_A_0 */
18 MUXCTL_UAA,
19 MUXCTL_UAB,
20 MUXCTL_UAC,
21 MUXCTL_UAD,
22 MUXCTL_UDA,
23 MUXCTL_RESERVED5,
24 MUXCTL_ATE,
25 MUXCTL_RM,
26
27 MUXCTL_ATB,
28 MUXCTL_RESERVED9,
29 MUXCTL_ATD,
30 MUXCTL_ATC,
31 MUXCTL_ATA,
32 MUXCTL_KBCF,
33 MUXCTL_KBCE,
34 MUXCTL_SDMMC1,
35
36 /* 16: APB_MISC_PP_PIN_MUX_CTL_B_0 */
37 MUXCTL_GMA,
38 MUXCTL_GMC,
39 MUXCTL_HDINT,
40 MUXCTL_SLXA,
41 MUXCTL_OWC,
42 MUXCTL_SLXC,
43 MUXCTL_SLXD,
44 MUXCTL_SLXK,
45
46 MUXCTL_UCA,
47 MUXCTL_UCB,
48 MUXCTL_DTA,
49 MUXCTL_DTB,
50 MUXCTL_RESERVED28,
51 MUXCTL_DTC,
52 MUXCTL_DTD,
53 MUXCTL_DTE,
54
55 /* 32: APB_MISC_PP_PIN_MUX_CTL_C_0 */
56 MUXCTL_DDC,
57 MUXCTL_CDEV1,
58 MUXCTL_CDEV2,
59 MUXCTL_CSUS,
60 MUXCTL_I2CP,
61 MUXCTL_KBCA,
62 MUXCTL_KBCB,
63 MUXCTL_KBCC,
64
65 MUXCTL_IRTX,
66 MUXCTL_IRRX,
67 MUXCTL_DAP1,
68 MUXCTL_DAP2,
69 MUXCTL_DAP3,
70 MUXCTL_DAP4,
71 MUXCTL_GMB,
72 MUXCTL_GMD,
73
74 /* 48: APB_MISC_PP_PIN_MUX_CTL_D_0 */
75 MUXCTL_GME,
76 MUXCTL_GPV,
77 MUXCTL_GPU,
78 MUXCTL_SPDO,
79 MUXCTL_SPDI,
80 MUXCTL_SDB,
81 MUXCTL_SDC,
82 MUXCTL_SDD,
83
84 MUXCTL_SPIH,
85 MUXCTL_SPIG,
86 MUXCTL_SPIF,
87 MUXCTL_SPIE,
88 MUXCTL_SPID,
89 MUXCTL_SPIC,
90 MUXCTL_SPIB,
91 MUXCTL_SPIA,
92
93 /* 64: APB_MISC_PP_PIN_MUX_CTL_E_0 */
94 MUXCTL_LPW0,
95 MUXCTL_LPW1,
96 MUXCTL_LPW2,
97 MUXCTL_LSDI,
98 MUXCTL_LSDA,
99 MUXCTL_LSPI,
100 MUXCTL_LCSN,
101 MUXCTL_LDC,
102
103 MUXCTL_LSCK,
104 MUXCTL_LSC0,
105 MUXCTL_LSC1,
106 MUXCTL_LHS,
107 MUXCTL_LVS,
108 MUXCTL_LM0,
109 MUXCTL_LM1,
110 MUXCTL_LVP0,
111
112 /* 80: APB_MISC_PP_PIN_MUX_CTL_F_0 */
113 MUXCTL_LD0,
114 MUXCTL_LD1,
115 MUXCTL_LD2,
116 MUXCTL_LD3,
117 MUXCTL_LD4,
118 MUXCTL_LD5,
119 MUXCTL_LD6,
120 MUXCTL_LD7,
121
122 MUXCTL_LD8,
123 MUXCTL_LD9,
124 MUXCTL_LD10,
125 MUXCTL_LD11,
126 MUXCTL_LD12,
127 MUXCTL_LD13,
128 MUXCTL_LD14,
129 MUXCTL_LD15,
130
131 /* 96: APB_MISC_PP_PIN_MUX_CTL_G_0 */
132 MUXCTL_LD16,
133 MUXCTL_LD17,
134 MUXCTL_LHP1,
135 MUXCTL_LHP2,
136 MUXCTL_LVP1,
137 MUXCTL_LHP0,
138 MUXCTL_RESERVED102,
139 MUXCTL_LPP,
140
141 MUXCTL_LDI,
142 MUXCTL_PMC,
143 MUXCTL_CRTP,
144 MUXCTL_PTA,
145 MUXCTL_RESERVED108,
146 MUXCTL_KBCD,
147 MUXCTL_GPU7,
148 MUXCTL_DTF,
149
150 MUXCTL_NONE = -1,
151};
152
153/*
154 * And this defines the order of the pullup/pulldown controls which are again
155 * in a different order
156 */
157enum pmux_pullid {
158 /* 0: APB_MISC_PP_PULLUPDOWN_REG_A_0 */
159 PUCTL_ATA,
160 PUCTL_ATB,
161 PUCTL_ATC,
162 PUCTL_ATD,
163 PUCTL_ATE,
164 PUCTL_DAP1,
165 PUCTL_DAP2,
166 PUCTL_DAP3,
167
168 PUCTL_DAP4,
169 PUCTL_DTA,
170 PUCTL_DTB,
171 PUCTL_DTC,
172 PUCTL_DTD,
173 PUCTL_DTE,
174 PUCTL_DTF,
175 PUCTL_GPV,
176
177 /* 16: APB_MISC_PP_PULLUPDOWN_REG_B_0 */
178 PUCTL_RM,
179 PUCTL_I2CP,
180 PUCTL_PTA,
181 PUCTL_GPU7,
182 PUCTL_KBCA,
183 PUCTL_KBCB,
184 PUCTL_KBCC,
185 PUCTL_KBCD,
186
187 PUCTL_SPDI,
188 PUCTL_SPDO,
189 PUCTL_GPSLXAU,
190 PUCTL_CRTP,
191 PUCTL_SLXC,
192 PUCTL_SLXD,
193 PUCTL_SLXK,
194
195 /* 32: APB_MISC_PP_PULLUPDOWN_REG_C_0 */
196 PUCTL_CDEV1,
197 PUCTL_CDEV2,
198 PUCTL_SPIA,
199 PUCTL_SPIB,
200 PUCTL_SPIC,
201 PUCTL_SPID,
202 PUCTL_SPIE,
203 PUCTL_SPIF,
204
205 PUCTL_SPIG,
206 PUCTL_SPIH,
207 PUCTL_IRTX,
208 PUCTL_IRRX,
209 PUCTL_GME,
210 PUCTL_RESERVED45,
211 PUCTL_XM2D,
212 PUCTL_XM2C,
213
214 /* 48: APB_MISC_PP_PULLUPDOWN_REG_D_0 */
215 PUCTL_UAA,
216 PUCTL_UAB,
217 PUCTL_UAC,
218 PUCTL_UAD,
219 PUCTL_UCA,
220 PUCTL_UCB,
221 PUCTL_LD17,
222 PUCTL_LD19_18,
223
224 PUCTL_LD21_20,
225 PUCTL_LD23_22,
226 PUCTL_LS,
227 PUCTL_LC,
228 PUCTL_CSUS,
229 PUCTL_DDRC,
230 PUCTL_SDC,
231 PUCTL_SDD,
232
233 /* 64: APB_MISC_PP_PULLUPDOWN_REG_E_0 */
234 PUCTL_KBCF,
235 PUCTL_KBCE,
236 PUCTL_PMCA,
237 PUCTL_PMCB,
238 PUCTL_PMCC,
239 PUCTL_PMCD,
240 PUCTL_PMCE,
241 PUCTL_CK32,
242
243 PUCTL_UDA,
244 PUCTL_SDMMC1,
245 PUCTL_GMA,
246 PUCTL_GMB,
247 PUCTL_GMC,
248 PUCTL_GMD,
249 PUCTL_DDC,
250 PUCTL_OWC,
251
252 PUCTL_NONE = -1
253};
254
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]255/* Convenient macro for defining pin group properties */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]256#define PINALL(pingrp, f0, f1, f2, f3, mux, pupd) \
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]257 { \
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]258 .funcs = { \
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]259 PMUX_FUNC_ ## f0, \
260 PMUX_FUNC_ ## f1, \
261 PMUX_FUNC_ ## f2, \
262 PMUX_FUNC_ ## f3, \
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]263 }, \
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]264 .ctl_id = mux, \
265 .pull_id = pupd \
266 }
267
268/* A normal pin group where the mux name and pull-up name match */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]269#define PIN(pingrp, f0, f1, f2, f3) \
270 PINALL(pingrp, f0, f1, f2, f3, MUXCTL_##pingrp, PUCTL_##pingrp)
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]271
272/* A pin group where the pull-up name doesn't have a 1-1 mapping */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]273#define PINP(pingrp, f0, f1, f2, f3, pupd) \
274 PINALL(pingrp, f0, f1, f2, f3, MUXCTL_##pingrp, PUCTL_##pupd)
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]275
276/* A pin group number which is not used */
277#define PIN_RESERVED \
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]278 PIN(NONE, RSVD1, RSVD2, RSVD3, RSVD4)
Stephen Warren8569b3a2014-03-21 12:28:51 -0600[diff] [blame]279
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]280#define DRVGRP(drvgrp) \
281 PINALL(drvgrp, RSVD1, RSVD2, RSVD3, RSVD4, MUXCTL_NONE, PUCTL_NONE)
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]282
Stephen Warrenf4df6052014-03-21 12:28:56 -0600[diff] [blame]283static const struct pmux_pingrp_desc tegra20_pingroups[] = {
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]284 PIN(ATA, IDE, NAND, GMI, RSVD4),
285 PIN(ATB, IDE, NAND, GMI, SDIO4),
286 PIN(ATC, IDE, NAND, GMI, SDIO4),
287 PIN(ATD, IDE, NAND, GMI, SDIO4),
288 PIN(CDEV1, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC),
289 PIN(CDEV2, OSC, AHB_CLK, APB_CLK, PLLP_OUT4),
290 PIN(CSUS, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK),
291 PIN(DAP1, DAP1, RSVD2, GMI, SDIO2),
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]292
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]293 PIN(DAP2, DAP2, TWC, RSVD3, GMI),
294 PIN(DAP3, DAP3, RSVD2, RSVD3, RSVD4),
295 PIN(DAP4, DAP4, RSVD2, GMI, RSVD4),
296 PIN(DTA, RSVD1, SDIO2, VI, RSVD4),
297 PIN(DTB, RSVD1, RSVD2, VI, SPI1),
298 PIN(DTC, RSVD1, RSVD2, VI, RSVD4),
299 PIN(DTD, RSVD1, SDIO2, VI, RSVD4),
300 PIN(DTE, RSVD1, RSVD2, VI, SPI1),
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]301
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]302 PINP(GPU, PWM, UARTA, GMI, RSVD4, GPSLXAU),
303 PIN(GPV, PCIE, RSVD2, RSVD3, RSVD4),
304 PIN(I2CP, I2C, RSVD2, RSVD3, RSVD4),
305 PIN(IRTX, UARTA, UARTB, GMI, SPI4),
306 PIN(IRRX, UARTA, UARTB, GMI, SPI4),
307 PIN(KBCB, KBC, NAND, SDIO2, MIO),
308 PIN(KBCA, KBC, NAND, SDIO2, EMC_TEST0_DLL),
309 PINP(PMC, PWR_ON, PWR_INTR, RSVD3, RSVD4, NONE),
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]310
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]311 PIN(PTA, I2C2, HDMI, GMI, RSVD4),
312 PIN(RM, I2C, RSVD2, RSVD3, RSVD4),
313 PIN(KBCE, KBC, NAND, OWR, RSVD4),
314 PIN(KBCF, KBC, NAND, TRACE, MIO),
315 PIN(GMA, UARTE, SPI3, GMI, SDIO4),
316 PIN(GMC, UARTD, SPI4, GMI, SFLASH),
317 PIN(SDMMC1, SDIO1, RSVD2, UARTE, UARTA),
318 PIN(OWC, OWR, RSVD2, RSVD3, RSVD4),
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]319
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]320 PIN(GME, RSVD1, DAP5, GMI, SDIO4),
321 PIN(SDC, PWM, TWC, SDIO3, SPI3),
322 PIN(SDD, UARTA, PWM, SDIO3, SPI3),
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]323 PIN_RESERVED,
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]324 PINP(SLXA, PCIE, SPI4, SDIO3, SPI2, CRTP),
325 PIN(SLXC, SPDIF, SPI4, SDIO3, SPI2),
326 PIN(SLXD, SPDIF, SPI4, SDIO3, SPI2),
327 PIN(SLXK, PCIE, SPI4, SDIO3, SPI2),
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]328
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]329 PIN(SPDI, SPDIF, RSVD2, I2C, SDIO2),
330 PIN(SPDO, SPDIF, RSVD2, I2C, SDIO2),
331 PIN(SPIA, SPI1, SPI2, SPI3, GMI),
332 PIN(SPIB, SPI1, SPI2, SPI3, GMI),
333 PIN(SPIC, SPI1, SPI2, SPI3, GMI),
334 PIN(SPID, SPI2, SPI1, SPI2_ALT, GMI),
335 PIN(SPIE, SPI2, SPI1, SPI2_ALT, GMI),
336 PIN(SPIF, SPI3, SPI1, SPI2, RSVD4),
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]337
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]338 PIN(SPIG, SPI3, SPI2, SPI2_ALT, I2C),
339 PIN(SPIH, SPI3, SPI2, SPI2_ALT, I2C),
340 PIN(UAA, SPI3, MIPI_HS, UARTA, ULPI),
341 PIN(UAB, SPI2, MIPI_HS, UARTA, ULPI),
342 PIN(UAC, OWR, RSVD2, RSVD3, RSVD4),
343 PIN(UAD, UARTB, SPDIF, UARTA, SPI4),
344 PIN(UCA, UARTC, RSVD2, GMI, RSVD4),
345 PIN(UCB, UARTC, PWM, GMI, RSVD4),
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]346
347 PIN_RESERVED,
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]348 PIN(ATE, IDE, NAND, GMI, RSVD4),
349 PIN(KBCC, KBC, NAND, TRACE, EMC_TEST1_DLL),
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]350 PIN_RESERVED,
351 PIN_RESERVED,
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]352 PIN(GMB, IDE, NAND, GMI, GMI_INT),
353 PIN(GMD, RSVD1, NAND, GMI, SFLASH),
354 PIN(DDC, I2C2, RSVD2, RSVD3, RSVD4),
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]355
356 /* 64 */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]357 PINP(LD0, DISPA, DISPB, XIO, RSVD4, LD17),
358 PINP(LD1, DISPA, DISPB, XIO, RSVD4, LD17),
359 PINP(LD2, DISPA, DISPB, XIO, RSVD4, LD17),
360 PINP(LD3, DISPA, DISPB, XIO, RSVD4, LD17),
361 PINP(LD4, DISPA, DISPB, XIO, RSVD4, LD17),
362 PINP(LD5, DISPA, DISPB, XIO, RSVD4, LD17),
363 PINP(LD6, DISPA, DISPB, XIO, RSVD4, LD17),
364 PINP(LD7, DISPA, DISPB, XIO, RSVD4, LD17),
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]365
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]366 PINP(LD8, DISPA, DISPB, XIO, RSVD4, LD17),
367 PINP(LD9, DISPA, DISPB, XIO, RSVD4, LD17),
368 PINP(LD10, DISPA, DISPB, XIO, RSVD4, LD17),
369 PINP(LD11, DISPA, DISPB, XIO, RSVD4, LD17),
370 PINP(LD12, DISPA, DISPB, XIO, RSVD4, LD17),
371 PINP(LD13, DISPA, DISPB, XIO, RSVD4, LD17),
372 PINP(LD14, DISPA, DISPB, XIO, RSVD4, LD17),
373 PINP(LD15, DISPA, DISPB, XIO, RSVD4, LD17),
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]374
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]375 PINP(LD16, DISPA, DISPB, XIO, RSVD4, LD17),
376 PINP(LD17, DISPA, DISPB, RSVD3, RSVD4, LD17),
377 PINP(LHP0, DISPA, DISPB, RSVD3, RSVD4, LD21_20),
378 PINP(LHP1, DISPA, DISPB, RSVD3, RSVD4, LD19_18),
379 PINP(LHP2, DISPA, DISPB, RSVD3, RSVD4, LD19_18),
380 PINP(LVP0, DISPA, DISPB, RSVD3, RSVD4, LC),
381 PINP(LVP1, DISPA, DISPB, RSVD3, RSVD4, LD21_20),
382 PINP(HDINT, HDMI, RSVD2, RSVD3, RSVD4, LC),
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]383
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]384 PINP(LM0, DISPA, DISPB, SPI3, RSVD4, LC),
385 PINP(LM1, DISPA, DISPB, RSVD3, CRT, LC),
386 PINP(LVS, DISPA, DISPB, XIO, RSVD4, LC),
387 PINP(LSC0, DISPA, DISPB, XIO, RSVD4, LC),
388 PINP(LSC1, DISPA, DISPB, SPI3, HDMI, LS),
389 PINP(LSCK, DISPA, DISPB, SPI3, HDMI, LS),
390 PINP(LDC, DISPA, DISPB, RSVD3, RSVD4, LS),
391 PINP(LCSN, DISPA, DISPB, SPI3, RSVD4, LS),
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]392
393 /* 96 */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]394 PINP(LSPI, DISPA, DISPB, XIO, HDMI, LC),
395 PINP(LSDA, DISPA, DISPB, SPI3, HDMI, LS),
396 PINP(LSDI, DISPA, DISPB, SPI3, RSVD4, LS),
397 PINP(LPW0, DISPA, DISPB, SPI3, HDMI, LS),
398 PINP(LPW1, DISPA, DISPB, RSVD3, RSVD4, LS),
399 PINP(LPW2, DISPA, DISPB, SPI3, HDMI, LS),
400 PINP(LDI, DISPA, DISPB, RSVD3, RSVD4, LD23_22),
401 PINP(LHS, DISPA, DISPB, XIO, RSVD4, LC),
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]402
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]403 PINP(LPP, DISPA, DISPB, RSVD3, RSVD4, LD23_22),
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]404 PIN_RESERVED,
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]405 PIN(KBCD, KBC, NAND, SDIO2, MIO),
406 PIN(GPU7, RTCK, RSVD2, RSVD3, RSVD4),
407 PIN(DTF, I2C3, RSVD2, VI, RSVD4),
408 PIN(UDA, SPI1, RSVD2, UARTD, ULPI),
409 PIN(CRTP, CRT, RSVD2, RSVD3, RSVD4),
410 PINP(SDB, UARTA, PWM, SDIO3, SPI2, NONE),
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]411
412 /* these pin groups only have pullup and pull down control */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]413 DRVGRP(CK32),
414 DRVGRP(DDRC),
415 DRVGRP(PMCA),
416 DRVGRP(PMCB),
417 DRVGRP(PMCC),
418 DRVGRP(PMCD),
419 DRVGRP(PMCE),
420 DRVGRP(XM2C),
421 DRVGRP(XM2D),
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]422};
Stephen Warrenf4df6052014-03-21 12:28:56 -0600[diff] [blame]423const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra20_pingroups;