| Tom Rini | ab06a53 | 2025-04-02 08:31:19 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ |
| 2 | /* |
| 3 | * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. |
| 4 | */ |
| 5 | |
| 6 | #ifndef _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H |
| 7 | #define _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H |
| 8 | |
| 9 | /* CMN PLL core clock. */ |
| 10 | #define CMN_PLL_CLK 0 |
| 11 | |
| 12 | /* The output clocks from CMN PLL of IPQ9574. */ |
| 13 | #define XO_24MHZ_CLK 1 |
| 14 | #define SLEEP_32KHZ_CLK 2 |
| 15 | #define PCS_31P25MHZ_CLK 3 |
| 16 | #define NSS_1200MHZ_CLK 4 |
| 17 | #define PPE_353MHZ_CLK 5 |
| 18 | #define ETH0_50MHZ_CLK 6 |
| 19 | #define ETH1_50MHZ_CLK 7 |
| 20 | #define ETH2_50MHZ_CLK 8 |
| 21 | #define ETH_25MHZ_CLK 9 |
| 22 | #endif |