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wdenked2ac4b2004-03-14 18:23:55 +00001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * 2003-2004 (c) MontaVista Software, Inc.
7 *
8 * Configuation settings for the ADS GraphicsClient+ board.
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
32#undef DEBUG
33
34/*
35 * The ADS GCPlus Linux boot ROM loads U-Boot into RAM at 0xc0200000.
36 * We don't actually init RAM in this case since we're using U-Boot as
37 * an secondary boot loader during Linux kernel development and testing,
38 * e.g. bootp/tftp download of the kernel is a far more convenient
39 * when testing new kernels on this target. However the ADS GCPlus Linux
40 * boot ROM leaves the MMU enabled when it passes control to U-Boot. So
wdenk336b2bc2005-04-02 23:52:25 +000041 * we use lowlevel_init (CONFIG_INIT_CRITICAL) to remedy that problem.
wdenked2ac4b2004-03-14 18:23:55 +000042 */
wdenk3d3d99f2005-04-04 12:44:11 +000043#undef CONFIG_SKIP_LOWLEVEL_INIT
44#define CONFIG_SKIP_RELOCATE_UBOOT 1
wdenked2ac4b2004-03-14 18:23:55 +000045
46/*
47 * High Level Configuration Options
48 * (easy to change)
49 */
50#define CONFIG_SA1110 1 /* This is an SA1100 CPU */
51#define CONFIG_GCPLUS 1 /* on an ADS GCPlus Board */
52
53#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
54
55#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
56#define CONFIG_SETUP_MEMORY_TAGS 1
57#define CONFIG_INITRD_TAG 1
58
59/*
60 * Size of malloc() pool
61 */
62#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
63#define CFG_GBL_DATA_SIZE 128 /* size rsrvd for initial data */
64
65
66/*
67 * Hardware drivers
68 */
69#define CONFIG_DRIVER_LAN91C96 /* we have an SMC9194 on-board */
70#define CONFIG_LAN91C96_BASE 0x100e0000
71
72/*
73 * select serial console configuration
74 */
75#define CONFIG_SERIAL3 1 /* we use SERIAL 3 on ADS GCPlus */
76
77/* allow to overwrite serial and ethaddr */
78#define CONFIG_ENV_OVERWRITE
79
80#define CONFIG_BAUDRATE 38400
81
82#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP)
83#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
84
85/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
86#include <cmd_confdefs.h>
87
88#define CONFIG_BOOTDELAY 3
89#define CONFIG_BOOTARGS "console=ttySA0,38400n8 mtdparts=sa1100-flash:1m@0(zImage),3m@1m(ramdisk.gz),12m@4m(userfs) root=/dev/nfs ip=bootp"
90#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm"
91#define CFG_AUTOLOAD "n" /* No autoload */
92
93#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
94#define CONFIG_KGDB_BAUDRATE 38400 /* speed to run kgdb serial port */
95#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
96#endif
97
98/*
99 * Miscellaneous configurable options
100 */
101#define CFG_LONGHELP /* undef to save memory */
102#define CFG_PROMPT "ADS GCPlus # " /* Monitor Command Prompt */
103#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
104#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
105#define CFG_MAXARGS 16 /* max number of command args */
106#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
107
108#define CFG_MEMTEST_START 0xc0400000 /* memtest works on */
109#define CFG_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */
110
111#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
112
113#define CFG_LOAD_ADDR 0xc0000000 /* default load address */
114
115#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
116#define CFG_CPUSPEED 0x0a /* set core clock to 206MHz */
117
118 /* valid baudrates */
119#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
120
121/*-----------------------------------------------------------------------
122 * Stack sizes
123 *
124 * The stack sizes are set up in start.S using the settings below
125 */
126#define CONFIG_STACKSIZE (128*1024) /* regular stack */
127#ifdef CONFIG_USE_IRQ
128#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
129#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
130#endif
131
132/*-----------------------------------------------------------------------
133 * Physical Memory Map
134 */
135#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 banks of DRAM */
136#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */
137#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */
138#define PHYS_SDRAM_2 0xc8000000 /* SDRAM Bank #2 */
139#define PHYS_SDRAM_2_SIZE 0x01000000 /* 16 MB */
140
141
142#define PHYS_FLASH_1 0x08000000 /* Flash Bank #1 */
143#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */
144#define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */
145#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
146
147#define CFG_FLASH_BASE PHYS_FLASH_1
148
149/*-----------------------------------------------------------------------
150 * FLASH and environment organization
151 */
152#if 1
153#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
154#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
155
156/* timeout values are in ticks */
157#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
158#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
159#else
wdenkc35ba4e2004-03-14 22:25:36 +0000160/* REVISIT: This doesn't work on ADS GCPlus just yet: */
wdenked2ac4b2004-03-14 18:23:55 +0000161#define CFG_FLASH_CFI 1 /* flash is CFI conformant */
162#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
163#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
164#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */
165#define CFG_FLASH_INCREMENT 0 /* there is only one bank */
166#define CFG_MAX_FLASH_SECT 128 /* max # of sectors on one chip */
wdenkc35ba4e2004-03-14 22:25:36 +0000167/*#define CFG_FLASH_PROTECTION 1 /--* hardware flash protection */
wdenked2ac4b2004-03-14 18:23:55 +0000168#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
169#endif
170
171#define CFG_ENV_IS_IN_FLASH 1
172#define CFG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE) /* Addr of Environment Sector */
173#define CFG_ENV_SIZE PHYS_FLASH_SECT_SIZE
174
175#endif /* __CONFIG_H */